Update on Algorithm

I think I now have the general idea for my algorithm. It's an STFT-based variational autoencoder that does a good job with reconstruction and sounds weird with a random latent space, which is exactly what I wanted. Now I can focus on reducing the network and using some toy examples for the next few codefests as AI had a hard time generating SystemVerilog for such a complicated network. Today's focus is on getting OpenLane up and running though.

OpenLane Newcomers and Colab Notebook

My background is a strange mix of high-level hardware and low-level fabrication process stuff, so this is somewhat new to me. Effectively what we want to do is use open-source tools to translate our HDL code to silicon. I'm just going to go the Colab route today as I've been more successful at that, but based on how long this is taking, it may be wise to do this on my computer. OpenLane takes a long time to download, and I don't want to have to do this every time.

I got the output of the example, and it looks like this:

Running a Version of My Algorithm

I had AI generate a slightly dumbed-down version of my decoder network:

class SimpleDecoder(nn.Module):
    def __init__(self, latent_dim=4):
        super().__init__()
        # 1) Fully-connected layer (4→4) with ReLU
        self.fc     = nn.Linear(latent_dim, latent_dim)
        # 2) ConvTranspose1d (1→1 channel) kernel=4, stride=2, pad=1
        self.deconv = nn.ConvTranspose1d(1, 1, kernel_size=4, stride=2, padding=1)
        # 3) Conv1d (1→1 channel) kernel=1
        self.conv1d = nn.Conv1d(1, 1, kernel_size=1)

I've attached my test bench and module code in my CF5 folder. Things were running well, but it said I needed to increase my die size. I had a very hard time finding out how to do this. I'm giving up on this and doing an easier network like this MLP:

module spm (
  input  wire signed [15:0] in0,
  input  wire signed [15:0] in1,
  input  wire signed [15:0] in2,
  input  wire signed [15:0] in3,
  output reg  signed [15:0] out0,
  output reg  signed [15:0] out1,
  output reg  signed [15:0] out2,
  output reg  signed [15:0] out3
);
  // intermediates
  reg signed [15:0] h0, h1, h2, h3;
  integer acc;
  always @* begin
    // FC1: identity weights=1, bias=0, then ReLU
    acc = in0 + in1 + in2 + in3;
    h0  = (acc < 0) ? 0 : acc;
    acc = in0 + in1 + in2 + in3;
    h1  = (acc < 0) ? 0 : acc;
    acc = in0 + in1 + in2 + in3;
    h2  = (acc < 0) ? 0 : acc;
    acc = in0 + in1 + in2 + in3;
    h3  = (acc < 0) ? 0 : acc;
    // FC2: again identity weights=1, bias=0
    out0 = h0 + h1 + h2 + h3;
    out1 = h0 + h1 + h2 + h3;
    out2 = h0 + h1 + h2 + h3;
    out3 = h0 + h1 + h2 + h3;
  end
endmodule

But nope, I got the stupid die size issue again. I've spent about an hour and a half on this issue. I'm just going to calculate the max frequency for the design that came with the Colab notebook.

Max Frequency

The following is the formula for our max frequency:

In our case it's 0.0534 μs as seen in the following, so a max frequency of around 100 MHz:

To Do in the Future

The following will help so I don't have to rely on online tools:

1. Get Icarus so I don't have to use EDAplayground
2. Get Vivado so I don't have to use OpenLane
3. Anything to avoid Colab's weird temporary file structure

See you next Wednesday.