GSoC'25 Project Ideas List - merledu/Google-Summer-of-Code GitHub Wiki

Welcome to the project ideas list for GSoC'25. You are allowed to choose any given project to work on with us or you can suggest your own idea as well.

We encourage you to join our Discord Server (gsoc-2025) to discuss ideas. Please use the recommended Proposal Format for all projects and you can see the detailed timeline here.

Project 01: Integrating TCAM IP into Chipyard via MMIO and RoCC Interfaces

Difficulty: Hard

Designation: 350 hours (large)

Required Skills & Tools: CHISEL, Verilog, C/C++.

Mentors: Shahzaib Kashif, Dr. Ali Ahmed, Sajjad Ahmed

Chat Channel: Discord Channel

Overview:

This project aims to integrate a Ternary Content Addressable Memory (TCAM) IP with our forked version of Chipyard as both a Memory-Mapped I/O (MMIO) peripheral and a RoCC (Rocket Custom Coprocessor) accelerator. The TCAM is a high-speed search memory that enables efficient lookup operations, making it useful for applications such as networking, security, and database acceleration.

The key objectives of this project are:

  1. MMIO Integration: Attach the TCAM IP as an MMIO device within the Chipyard SoC. This will allow the core to communicate with the TCAM using standard memory operations.
  2. RoCC Integration: Implement the TCAM as a RoCC accelerator, leveraging the Rocket Core’s RoCC interface for direct communication with the processor.
  3. Software Interface: Develop a user-space software library or API that enables applications to interact with the TCAM seamlessly. This should include functions for writing, reading, and searching within the TCAM.
  4. Testing & Verification: Validate the correctness and performance of the integration by writing test programs that run on the generated SoC containing (Core + TCAM as MMIO) and (Core + TCAM as RoCC).

Expected Outcomes:

  • A fully integrated TCAM IP with Chipyard, accessible via both MMIO and RoCC.
  • A software library that provides an easy-to-use interface for interacting with TCAM.
  • Test programs that demonstrate TCAM functionality on the generated SoC.
  • Documentation to help future contributors extend or modify the TCAM integration.

Skills Required:

  • Familiarity with RISC-V and Chipyard framework.
  • Experience with Chisel/Verilog for hardware design.
  • Knowledge of SoC integration, MMIO, and RoCC interfaces.
  • Proficiency in C/C++ for writing the software interface.

Project 02: A.U.T.O.V.A.R. - Automated UVM Tuning Orchestrated Via AI Reasoning

Difficulty: Hard

Designation: 350 hours (large)

Required Skills & Tools: UVM, SystemVerilog, Python, Machine Learning, NLP, Transformers, Reinforcement Learning, Regression Testing, Hardware Verification.

Mentors: Dr. Farhan Ahmed Karim

Chat Channel: Discord Channel

Overview:

A.U.T.O.V.A.R. is an AI-powered framework designed to automate the modification of UVM components (drivers, monitors, scoreboards, sequences) based on evolving DUT specifications. By leveraging NLP and ML, the system extracts key parameters from DUT documentation and updates verification environments accordingly. Reinforcement learning ensures that the generated UVM components are validated against regression tests and optimized for coverage. This project aims to minimize manual effort, reduce human error, and accelerate the verification cycle in hardware design.

Methodology

  1. DUT Specification Analysis
    • Use natural language processing (NLP) and machine learning (ML) to parse DUT specifications (e.g. interface documents, or protocol standards).
    • Extract key parameters: signal names, timing requirements, protocol rules, and transaction formats.
  2. UVM Component Modification
    • Train an A.I. model (e.g., a transformer-based architecture) to map DUT changes to UVM component updates:
      • Drivers/Monitors: Adjust transaction generation/collection logic based on new signal timing or protocol rules.
      • Scoreboards: Update reference models and error-checking algorithms to reflect DUT functionality.
      • Sequences: Regenerate test sequences to cover new scenarios or constraints.
    • Use reinforcement learning (RL) to validate modified components against regression tests and optimize for coverage.
    • Enable real-time feedback loops: Test failures trigger iterative AI refinement of UVM components.

Expected Outcomes:

  • AI-powered parser for DUT specifications using NLP
  • Automated UVM component adaptation based on DUT changes
  • Integration of reinforcement learning for optimizing verification environments
  • Real-time feedback loops for iterative UVM refinement
  • Improved verification efficiency and reduced manual workload

Project 03: AEGIS - AI-Enhanced Generation of Intelligent Scenarios

Difficulty: Hard

Designation: 350 hours (large)

Required Skills & Tools: UVM, SystemVerilog, Python, Machine Learning, NLP, Reinforcement Learning, Hardware Verification, ASIC/FPGA Design, AXI/PCIe/USB Protocols.

Mentors: Dr. Farhan Ahmed Karim, Shahzaib Kashif

Chat Channel: Discord Channel

Overview

AEGIS is an AI-driven framework designed to automate the generation of optimized test cases for hardware verification. Using NLP, the system extracts key features from DUT specifications and synthesizes test scenarios targeting corner cases, protocol compliance, and functional coverage. Reinforcement learning helps prioritize high-impact tests to maximize verification efficiency. The generated test cases are integrated into UVM environments with automated sequences, scoreboard checks, and assertions.

Methodology

  1. DUT Specification Parsing
    • Use NLP to analyze DUT specifications (e.g. protocol standards, or natural-language requirements).
    • Extract critical features: interfaces, timing diagrams, protocol rules, and functional modes.
  2. Test Case Synthesis
    • Train an A.I. model to map DUT specifications to test scenarios, including:
      • Corner Cases: Stress tests for boundary conditions (e.g., FIFO overflow, clock domain crossings).
      • Protocol Compliance: Tests for adherence to standards like AXI, PCIe, or USB.
      • Functional Coverage: Scenarios targeting untested logic in the DUT.
    • Use reinforcement learning (RL) to prioritize high-impact tests that maximize coverage metrics.
  3. Integration with Verification Environment
    • Generate UVM-compatible test sequences, scoreboard checks, and assertions.

Expected Outcomes

  • AI-powered DUT specification parser using NLP
  • Automated test scenario generation covering corner cases, protocol compliance, and functional coverage
  • Reinforcement learning-based test prioritization for enhanced coverage
  • UVM-compatible test sequences, assertions, and scoreboard integration
  • Improved verification speed and reduced manual test generation effort

Project 04: AURUM - Automated UVM Reference of Userspec Model

Difficulty: Hard

Designation: 350 hours (large)

Required Skills & Tools: UVM, SystemVerilog, Python, NLP, Machine Learning, Formal Verification, SMT Solvers, Hardware Verification, Behavioral Modeling.

Mentors: Talha Ahmed

Chat Channel: Discord Channel

Overview

AURUM is an AI-driven framework that automates the generation of high-accuracy golden/reference models from DUT specifications. Using NLP, the system extracts functional requirements, protocols, and constraints to generate executable golden models. AI-based behavioral cloning ensures high-fidelity mapping from specifications to code, while self-validation techniques, including formal verification and adaptive learning, ensure correctness. This approach reduces manual model development efforts, minimizes human error, and accelerates verification cycles.

Methodology

  1. Specification Analysis
    • NLP Parsing: Extract functional requirements, protocols, and timing constraints from DUT specifications (text documents, or UML diagrams).
    • Contextual Understanding: Use A.I. model to infer implicit requirements (e.g., "FIFO depth = 16" implies overflow/underflow conditions).
  2. Model Generation
    • Code Synthesis: Convert parsed specifications into executable golden models.
      • Example: Translate "32-bit CRC32 calculator" into a Python function using the IEEE 802.3 polynomial.
    • Behavioral Cloning: Train A.I. models on existing golden model-DUT pairs to learn specification-to-code mappings.
  3. Self-Validation
    • Consistency Checks: Use formal methods (e.g., SMT solvers) to verify AI-generated models against specifications.
    • Adaptive Learning: Refine models using test failures and coverage feedback from verification environments.

Expected Outcomes

  • AI-powered specification parser to extract DUT functionalities
  • Automated synthesis of golden/reference models from specifications
  • Behavioral cloning for learning specification-to-code mappings
  • Formal verification and self-validation using SMT solvers
  • Integration with UVM-based verification environments

Project 05: General Test Bench for RISC-V CPUs Using PYUVM

Difficulty: Medium

Designation: 350 hours (large)

Required Skills & Tools: UVM, SystemVerilog, Python, Functional Verification, Hardware Verification, Behavioral Modeling.

Mentors: Zeeshan Rafique, Usman Zain, Auringzaib Sabir

Chat Channel: Discord Channel

Overview

With the increasing adoption of RISC-V as an open-source Instruction Set Architecture (ISA), there is a growing need for effective and reusable verification methodologies. This project aims to develop a general test bench for RISC-V CPUs using pyuvm, a Python-based Universal Verification Methodology (UVM) framework. The goal is to create a structured, reusable, and automated verification environment that facilitates CPU validation, functional correctness, and compliance testing.

Benefits to the Community

  • Unified Verification Framework : Provides a consistent and reusable test environment across different RISC-V CPU implementations.
  • Accessibility: Uses Python and pyuvm, making UVM-based verification more accessible to a broader audience.
  • Automation: Supports automated test execution and result analysis, reducing the manual effort in CPU verification.
  • Compliance and Debugging: Ensures conformance with the RISC-V specification and aids in debugging CPU designs.

Methodology

Test Bench Architecture:

  • Modular design with transaction-level modeling.
  • Sequence generation for instruction execution.
  • Coverage collection and analysis.
  • Integration with RISC-V Simulators:
  • Support for Verilator and Spike.
  • Automated simulation result analysis.

Test Suite Development:

  • Basic functional tests (ALU, control flow, memory access, etc.).
  • Compliance tests for RISC-V ISA validation.
  • Directed and random instruction sequences for robustness.

Automation and Reporting:

  • Python-based scripting for test execution.
  • Logging and result visualization.

Expected Outcomes

  • A generic test bench framework for RISC-V CPUs using pyuvm.
  • A set of reusable test cases covering core CPU functionalities.
  • Integration with open-source RISC-V simulators (e.g., Verilator, Spike).
  • Scripts for automated testing and reporting.
  • Documentation on usage and extension.

Skills Required to standout:

  • Familiarity with RISC-V architecture and CPU design.
  • Experience with Python-based verification frameworks.
  • Knowledge of UVM and hardware simulation tools.
  • Basic understanding of Formal verification.
  • Understanding of Verilator, Spike, or other RISC-V simulators (preferred).

Future Enhancements:

  • Extend coverage to advanced RISC-V features (e.g., vector extensions, privileged mode testing).
  • Integrate with formal verification tools.
  • Support multi-core RISC-V CPU verification.

References:

Project 06: Running Secure and Vectorized Applications on SoC-Now

Difficulty: Medium-Hard

Designation: 350 hours (large)

Required Skills: CHISEL, Verilog, RISC-V, C/C++, Python

Mentors: Shahzaib Kashif

Chat Channel: Discord Channel

Overview

This project aims to integrate and test real-world applications on SoC-Now, a CHISEL-based SoC generator that includes:

  • NucleusRV (a parameterized RISC-V Core)
  • Vaquita (an RVV-compatible Vector Coprocessor)
  • Baby Kyber (a Post-Quantum Cryptography Accelerator)
  • Caravan (a parameterized bus generator)
  • Jigsaw (a parameterized peripheral generator)

The goal is to develop and execute high-performance applications that leverage the vector computing (RVV) capabilities of Vaquita and the post-quantum cryptography acceleration provided by Baby Kyber.

Methodology

  1. Implement Software Applications for the SoC-Now platform.
    • Vectorized Image Processing (e.g., Edge Detection, Convolution) using Vaquita.
    • ML Inference Acceleration (Matrix Multiplications, TinyML models) with Vaquita.
    • Post-Quantum Cryptography (Secure Key Exchange, Encryption/Decryption) with Baby Kyber.
    • Hybrid Applications (Secure AI with encrypted data using Kyber & Vaquita).
  2. Modify and Extend the SoC-Now software stack to support these applications.
  3. Benchmark Performance Gains by comparing execution times with and without accelerators.
  4. Document and Package the Work so it can be easily used by the RISC-V community.

Expected Outcomes

  • A set of high-performance applications running on SoC-Now.
  • Performance benchmarks comparing NucleusRV, Vaquita, and Baby Kyber acceleration.
  • Documentation and tutorials to help future developers integrate applications.
  • Code contributions to the open-source SoC-Now repository.

Skills Required

  • Familiarity with RISC-V architecture and CHISEL-based SoC design.
  • Understanding of RVV (RISC-V Vector Extensions) and cryptographic accelerators.
  • Experience with C/C++ for embedded programming.
  • Knowledge of Python for benchmarking and performance analysis.