Skip to content

Device address space

Jump to bottom
Alex Forencich edited this page Feb 2, 2021 · 2 revisions

The Corundum address space is designed to be flexible to adjust to FPGA application requirements. The driver is loosely coupled to the FPGA design: the address space configuration is exposed to the driver through a number of informational registers, permitting the driver to automatically determine the layout without any board or design specific magic numbers or manual changes to the driver code.

The driver prints out many of the address space parameters during probe, for example:

mqnic 0000:01:00.0: mqnic PCI probe
mqnic 0000:01:00.0: enabling device (0000 -> 0002)
mqnic 0000:01:00.0: FW ID: 0x00000000
mqnic 0000:01:00.0: FW version: 0.1
mqnic 0000:01:00.0: Board ID: 0x10ee9118
mqnic 0000:01:00.0: Board version: 0.1
mqnic 0000:01:00.0: PHC count: 1
mqnic 0000:01:00.0: PHC offset: 0x00000200
mqnic 0000:01:00.0: IF count: 2
mqnic 0000:01:00.0: IF stride: 0x00800000
mqnic 0000:01:00.0: IF CSR offset: 0x00040000
mqnic 0000:01:00.0: Resetting Alveo CMS
mqnic 0000:01:00.0: Read 2 MACs from Alveo BMC
mqnic 0000:01:00.0: registered PHC (index 6)
mqnic 0000:01:00.0: Creating interface 0
mqnic 0000:01:00.0: IF ID: 0x00000000
mqnic 0000:01:00.0: IF features: 0x00000701
mqnic 0000:01:00.0: Event queue count: 32
mqnic 0000:01:00.0: Event queue offset: 0x00080000
mqnic 0000:01:00.0: TX queue count: 8192
mqnic 0000:01:00.0: TX queue offset: 0x00100000
mqnic 0000:01:00.0: TX completion queue count: 8192
mqnic 0000:01:00.0: TX completion queue offset: 0x00200000
mqnic 0000:01:00.0: RX queue count: 256
mqnic 0000:01:00.0: RX queue offset: 0x00300000
mqnic 0000:01:00.0: RX completion queue count: 256
mqnic 0000:01:00.0: RX completion queue offset: 0x00380000
mqnic 0000:01:00.0: Port count: 1
mqnic 0000:01:00.0: Port offset: 0x00400000
mqnic 0000:01:00.0: Port stride: 0x00100000
mqnic 0000:01:00.0: Max desc block size: 8
mqnic 0000:01:00.0: Port ID: 0x00000000
mqnic 0000:01:00.0: Port features: 0x00000701
mqnic 0000:01:00.0: Port MTU: 16384
mqnic 0000:01:00.0: Scheduler count: 1
mqnic 0000:01:00.0: Scheduler offset: 0x00080000
mqnic 0000:01:00.0: Scheduler stride: 0x00080000
mqnic 0000:01:00.0: Scheduler type: 0x00000000
mqnic 0000:01:00.0: Creating interface 1
mqnic 0000:01:00.0: IF ID: 0x00000000
mqnic 0000:01:00.0: IF features: 0x00000701
mqnic 0000:01:00.0: Event queue count: 32
mqnic 0000:01:00.0: Event queue offset: 0x00080000
mqnic 0000:01:00.0: TX queue count: 8192
mqnic 0000:01:00.0: TX queue offset: 0x00100000
mqnic 0000:01:00.0: TX completion queue count: 8192
mqnic 0000:01:00.0: TX completion queue offset: 0x00200000
mqnic 0000:01:00.0: RX queue count: 256
mqnic 0000:01:00.0: RX queue offset: 0x00300000
mqnic 0000:01:00.0: RX completion queue count: 256
mqnic 0000:01:00.0: RX completion queue offset: 0x00380000
mqnic 0000:01:00.0: Port count: 1
mqnic 0000:01:00.0: Port offset: 0x00400000
mqnic 0000:01:00.0: Port stride: 0x00100000
mqnic 0000:01:00.0: Max desc block size: 8
mqnic 0000:01:00.0: mqnic_start_port on port 0
mqnic 0000:01:00.0: Port ID: 0x00000000
mqnic 0000:01:00.0: Port features: 0x00000701
mqnic 0000:01:00.0: Port MTU: 16384
mqnic 0000:01:00.0: Scheduler count: 1
mqnic 0000:01:00.0: Scheduler offset: 0x00080000
mqnic 0000:01:00.0: Scheduler stride: 0x00080000
mqnic 0000:01:00.0: Scheduler type: 0x00000000
mqnic 0000:01:00.0: mqnic_start_port on port 1

These parameters describe the following layout:

00000000 - 0003FFFF NIC CSRs
    00000020 IF_COUNT = 2
    00000024 IF_STRIDE = 0x0080000
    0000002C IF_CSR_OFFSET = 0x00040000
00040000 - 007FFFFF Interface 0
    00040000 - 0007FFFF Interface CSRs
        00040014 EVENT_QUEUE_OFFSET = 0x00080000
        00040024 TX_QUEUE_OFFSET = 0x00100000
        0004002C TX_CPL_QUEUE_OFFSET = 0x00200000
        00040034 RX_QUEUE_OFFSET = 0x00300000
        0004003C RX_CPL_QUEUE_OFFSET = 0x00380000
        00040040 PORT_COUNT = 1
        00040044 PORT_OFFSET = 0x00400000
        00040048 PORT_STRIDE = 0x00100000
    00080000 - 000FFFFF Event queues
    00100000 - 001FFFFF TX queues
    00200000 - 002FFFFF TX completion queues
    00300000 - 0037FFFF RX queues
    00380000 - 003FFFFF RX completion queues
    00400000 - 004FFFFF Port 0
        00400000 - 0047FFFF Port 0 CSRs
            00400010 SCHED_COUNT = 1
            00400014 SCHED_OFFSET = 0x00080000
            00400018 SCHED_STRIDE = 0x00080000
        00480000 - 004FFFFF Port 0 scheduler 0
    00500000 - 005FFFFF Port 1 (unused)
    00600000 - 006FFFFF Port 2 (unused)
    00700000 - 007FFFFF Port 3 (unused)
00800000 - 0083FFFF NIC CSRs (alias)
00840000 - 0084FFFF Interface 1
    00840000 - 0087FFFF Interface CSRs
        00840014 EVENT_QUEUE_OFFSET = 0x00080000
        00840024 TX_QUEUE_OFFSET = 0x00100000
        0084002C TX_CPL_QUEUE_OFFSET = 0x00200000
        00840034 RX_QUEUE_OFFSET = 0x00300000
        0084003C RX_CPL_QUEUE_OFFSET = 0x00380000
        00840040 PORT_COUNT = 1
        00840044 PORT_OFFSET = 0x00400000
        00840048 PORT_STRIDE = 0x00100000
    00880000 - 008FFFFF Event queues
    00900000 - 009FFFFF TX queues
    00A00000 - 00AFFFFF TX completion queues
    00B00000 - 00B7FFFF RX queues
    00B80000 - 00BFFFFF RX completion queues
    00C00000 - 00CFFFFF Port 0
        00C00000 - 00C7FFFF Port 0 CSRs
            00C00010 SCHED_COUNT = 1
            00C00014 SCHED_OFFSET = 0x00080000
            00C00018 SCHED_STRIDE = 0x00080000
        00C80000 - 00CFFFFF Port 0 scheduler 0
    00D00000 - 00DFFFFF Port 1 (unused)
    00E00000 - 00EFFFFF Port 2 (unused)
    00F00000 - 00FFFFFF Port 3 (unused)
Clone this wiki locally