SV Interview Questions - ZishanManna/interview-prep-wiki GitHub Wiki

SystemVerilog Interview Questions

Question 1: What is the difference between initial and always blocks in SystemVerilog?

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  • initial Block: Executes once at the start of the simulation and is used for setting up initial values.
  • always Block: Continuously repeats whenever the sensitivity list is active and is typically used for describing both combinational and sequential logic.

Question 2: What is the difference between logic and wire in SystemVerilog?

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  • wire: Represents a continuous assignment, cannot hold a value.
  • logic: A SystemVerilog data type that can be used as a signal or variable and is compatible for both combinational and sequential logic.

Question 3: What are interface and modport in SystemVerilog?

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  • interface: A construct used to group related signals together, making connections between modules easier.
  • modport: Defines specific access restrictions (read, write, or both) for signals in an interface.

Question 4: What is the difference between assert and assume in SystemVerilog?

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  • assert: Checks a condition during simulation and throws an error if the condition is not met.
  • assume: Specifies a condition that should always hold true for formal verification tools, used to define constraints on inputs.

Question 5: What are unique and priority keywords? When should they be used?

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  • unique: Ensures that no two case items match at the same time. If no case item matches, it raises a warning.
  • priority: Indicates that higher-priority items should be evaluated first. If no case item matches, it doesn’t raise a warning.

Question 6: What is the difference between blocking and non-blocking assignments?

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  • Blocking (=): Statements execute sequentially. The right-hand side value is immediately assigned to the left-hand side.
  • Non-blocking (<=): The evaluation of the right-hand side occurs immediately, but the assignment to the left-hand side is postponed until the end of the time step.

Question 7: Explain the difference between fork-join and fork-join_none in SystemVerilog?

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  • fork-join: Executes all threads in parallel and waits for all of them to complete before proceeding.
  • fork-join_none: Executes all threads in parallel but does not wait for any of them to complete.

Question 8: What are covergroups in SystemVerilog?

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  • Covergroups are used for functional coverage analysis to track coverage points and ensure that various scenarios are tested.

Question 9: What is a constraint in SystemVerilog?

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  • Constraints are rules that control randomization, specifying conditions that the randomly generated values must meet.

Question 10: What are typedef and enum in SystemVerilog?

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  • typedef: Used to create an alias for a data type.
  • enum: Defines an enumerated data type with symbolic names representing integer values.

Question 11: How do you define a parameter in SystemVerilog?

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  • parameter: Used to define constants in a module that can be overridden during module instantiation.

Question 12: What is a virtual interface in SystemVerilog?

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  • A virtual interface is a reference to a physical interface, used primarily for passing interfaces to classes for testbenches and verification environments.

Question 13: What is a randomize() function?

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  • randomize() is used in SystemVerilog to generate random values for the variables within a class. You can apply constraints to control the randomization.

Question 14: What are the different types of coverpoints?

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  • Coverpoints can be of two types:
    1. Cross Coverage: Defines coverage points across multiple variables.
    2. Simple Coverage: Tracks values or conditions for a single variable.

Question 15: What are mailbox and queue in SystemVerilog?

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  • Mailbox: A communication mechanism used for sending and receiving messages between parallel processes.
  • Queue: A dynamic array that can be resized at runtime and used for storing ordered data.

Question 16: What is a class in SystemVerilog?

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  • A class is a user-defined data type that encapsulates variables and methods (functions and tasks). It supports object-oriented programming concepts.

Question 17: What is the use of unique case and priority case?

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  • unique case: Checks for mutually exclusive conditions.
  • priority case: Prioritizes checking of the case items in order.

Question 18: What is uvm_component?

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  • A uvm_component is a base class in the UVM framework used for building verification components like drivers, monitors, and agents.

Question 19: Explain the concept of process control in SystemVerilog.

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  • Process control involves using constructs like disable, wait, join, and fork to control the execution of processes in parallel and sequential code blocks.

Question 20: What is coverage in SystemVerilog?

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  • Coverage refers to the analysis of how well the simulation tests cover various functional aspects, ensuring all scenarios are verified. It includes code coverage, functional coverage, and assertion coverage.

Question 21: What is the difference between interface and struct in SystemVerilog?

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  • Interface: Groups related signals and allows for easier connectivity between modules. It also supports advanced features like modport and clocking blocks.
  • Struct: A composite data type used to bundle multiple variables of different types under a single name, useful for storing data rather than connectivity.

Question 22: What is a typedef enum and when would you use it?

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  • typedef enum: Allows defining a new enumerated type with symbolic names for each value. It's useful for state machines and defining symbolic states for better readability and code maintainability.

Question 23: How do you implement a state machine in SystemVerilog?

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  1. Define the states using typedef enum.
  2. Use an always_ff block to implement state transitions.
  3. Use another always_comb block to define the next state logic and output behavior.

Question 24: What is the purpose of bind in SystemVerilog?

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  • The bind construct is used to associate external verification code (e.g., assertions or cover properties) with a module instance without modifying the module’s source code.

Question 25: What are the differences between program blocks and module blocks?

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  • Program Block: Used in testbenches for sequential simulation. It’s event-driven and executes in the reactive region.
  • Module Block: Represents hardware components and executes in the active region.

Question 26: What are Clocking Blocks? Why are they needed?

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  • Clocking Blocks: Used to group related signals driven or sampled by a common clock in a testbench. They help synchronize between design and testbench signals and avoid race conditions.

Question 27: What is wildcard equality and wildcard case?

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  • Wildcard Equality (===, !==): Compares values with unknowns (x or z). It returns true if unknowns match or if both operands have x in the same position.
  • Wildcard Case: Allows case statements to match patterns with x and z values.

Question 28: What are properties in SystemVerilog?

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  • Properties: A high-level construct used in SystemVerilog Assertions (SVA) to describe temporal relationships between signals. They are used within assert and assume statements.

Question 29: Explain the concept of task and function in SystemVerilog.

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  • Task: Can include time-consuming statements (e.g., #, @). Can return zero or more values.
  • Function: Executes in zero simulation time and returns a single value. Cannot include time-consuming statements.

Question 30: What is a static and automatic variable in SystemVerilog?

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  • Static Variable: Retains its value between calls.
  • Automatic Variable: Does not retain its value between calls. It is re-created every time the scope is entered, useful for reentrant tasks and functions.

Question 31: How do you perform randomization in SystemVerilog?

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  • Use the randomize() method on class variables.
  • Apply constraint blocks to limit the values.
  • Use the void' randomize() syntax to randomize inline variables.

Question 32: What is assertion coverage in SystemVerilog?

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  • Assertion Coverage: Tracks which assertions in the design have been triggered during simulation. It helps ensure that all expected conditions are verified.

Question 33: What is the uvm_sequence class?

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  • The uvm_sequence class is a base class in UVM used to generate and manage stimulus for a testbench. Sequences define a series of transactions to be sent to a driver.

Question 34: Explain call by reference vs call by value in SystemVerilog.

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  • Call by Value: A copy of the actual value is passed, changes made in the called function do not affect the original variable.
  • Call by Reference: A reference to the actual variable is passed, changes made in the called function affect the original variable.

Question 35: What is a factory pattern in UVM?

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  • The factory pattern allows for creating objects dynamically in UVM. It provides flexibility for changing the class type of objects in a testbench without modifying the source code.

Question 36: What is the role of clocking blocks in UVM?

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  • In UVM, clocking blocks are used to control signal timing between the design and testbench, ensuring race-free signal sampling and driving in testbenches.

Question 37: How is a cover property different from a covergroup?

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  • Cover Property: Focuses on checking specific temporal properties.
  • Covergroup: Tracks values and transitions of variables to evaluate functional coverage.

Question 38: How can you pass parameters to classes in SystemVerilog?

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  • Use parameterized classes by defining the parameters in the class header using the parameter keyword.

Question 39: What is a process in SystemVerilog?

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  • A process is any always, initial, fork, or join block in SystemVerilog. It represents a parallel thread of execution within a module or testbench.

Question 40: What is the purpose of constraint soft in SystemVerilog?

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  • The constraint soft keyword is used to define a constraint that can be overridden by other constraints. It provides flexibility in randomization by allowing other constraints to take precedence.

Question 41: What is the difference between solve and soft constraints?

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  • solve Constraint: Specifies the order in which random variables should be solved. For example, solve a before b means a is solved first.
  • soft Constraint: Can be overridden by stronger constraints. If no conflicting constraints exist, the soft constraint is applied.

Question 42: What is the difference between rand and randc in SystemVerilog?

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  • rand: Generates random values without considering previous values.
  • randc: Generates cyclic random values, ensuring that all possible values are produced before repeating any value.

Question 43: How do you create hierarchical constraints in SystemVerilog?

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  • Use the constraint keyword inside a class or struct and reference nested fields or parent class variables.
  • For example: 
    class A;
  rand int a;
  constraint a_c { a > 0; }
endclass

class B extends A;
  rand int b;
  constraint b_c { b > a; }  // Hierarchical constraint
endclass

Question 44: What are implication constraints and how are they used?

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  • Implication Constraints are defined using the -> operator and are used to express dependencies between variables.
  • For example: 
    constraint c { a == 1 -> b == 0; }
    This constraint means: If a is 1, then b must be 0.

Question 45: How can you use foreach constraints in SystemVerilog?

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  • foreach constraints are used to apply a constraint on each element of an array.
  • For example: 
    rand bit [3:0] array[5];
constraint c { foreach(array[i]) array[i] < 5; }
    This constraint ensures each element in the array is less than 5.

Question 46: How do you define a constraint block for a particular value?

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  • Use inside constraints for restricting the range or specific values: 
    rand int x;
constraint c { x inside {1, 3, 5, 7}; }
    This constraint restricts x to the values 1, 3, 5, or 7.

Question 47: What is random stability? How is it achieved?

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  • Random Stability: Ensures that random values remain consistent across multiple simulations.
  • It is achieved using the srandom(seed) method to set a specific seed value.

Question 48: What is a disable soft constraint?

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  • disable soft removes the effect of a soft constraint. It overrides the soft constraint temporarily in a local context.

Question 49: What are assert, assume, and cover?

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  • assert: Checks a condition during simulation. If the condition fails, it triggers an error.
  • assume: Specifies assumptions for formal verification. Used to define constraints on inputs.
  • cover: Tracks specific points in the simulation to ensure coverage of particular scenarios.

Question 50: How do you implement a disable iff condition in assertions?

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  • Use disable iff to disable the assertion check when a specific condition is met.
  • For example: 
    assert property (@(posedge clk) disable iff (reset) (a == b));
    This assertion is disabled whenever reset is high.

Question 51: How do you create a sequence in SystemVerilog assertions?

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  • Use the sequence keyword to define a temporal sequence.
  • For example: 
    sequence seq_a;
  @(posedge clk) a ##1 b ##2 c;  // Sequence defines that `a` occurs, followed by `b` 1 cycle later, and `c` 2 cycles later.
endsequence

Question 52: What is overlapping and non-overlapping implications?

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  • Overlapping Implication (|->): Triggers the consequent expression at the same time as the antecedent.
  • Non-Overlapping Implication (|=>): Triggers the consequent expression one clock cycle after the antecedent.

Question 53: What are concurrent assertions?

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  • Concurrent Assertions: Evaluate temporal conditions over multiple clock cycles. Defined using property, sequence, and assert blocks. They are triggered at specific simulation times.

Question 54: How do you use local variable declarations in assertions?

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  • Local variables in assertions are used to hold temporary values.
  • For example: 
    property p1;
  int local_var;
  @(posedge clk) (a == 1) |-> (local_var = b);
endproperty

Question 55: Explain covergroup and coverpoint in SystemVerilog.

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  • Covergroup: A group of coverpoints and cross statements used to capture functional coverage.
  • Coverpoint: Monitors specific variables and tracks value hits.

Question 56: What is a cover cross?

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  • A cross statement captures the relationship between two or more coverpoints.
  • For example: 
    covergroup cg;
  coverpoint a;
  coverpoint b;
  cross a, b;  // Cross coverage between `a` and `b`
endgroup

Question 57: How do you write an immediate assertion?

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  • Immediate Assertions: Use assert without temporal logic. They are evaluated immediately when encountered.
  • Example: 
    assert(a == b) else $fatal("Assertion failed: a != b");

Question 58: How do you randomize a dynamic array in SystemVerilog?

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  • Randomize using the randomize() function with foreach constraints: 
    rand int dyn_array[];
constraint size_c { dyn_array.size() == 10; }
constraint val_c { foreach(dyn_array[i]) dyn_array[i] < 50; }

Question 59: What are uniqueness constraints?

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  • Uniqueness Constraints ensure that multiple random variables are assigned unique values: 
    rand int a, b, c;
constraint unique_c { unique {a, b, c}; }

Question 60: How do you apply constraints conditionally?

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  • Use if and inside conditions in constraint blocks: 
    rand int x, y;
constraint c {
  if (y > 0) x inside {1, 2, 3};
}
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