Unibus Adapter Exerciser - KS10FPGA/KS10FPGA GitHub Wiki

The Unibus Adapter Exerciser (UBE) is a device that is used to test the KS10 Unibus Adapter. As such, the UBE has been implemented as required to test the functionality of the UBA.

There is virtually no engineering information available for the UBE available. The information provided here is reverse engineered from the DSUBA software and documentation.

There are 12 known UBE devices. The UBE device is fully parameterized and can be configured as any of the UBE devices. The current firmware implements the first 4 UBE devices attached to UBA4. The DSUBA diagnostic searches for the UBE devices from the lowest IO address to the highest IO address and calls the first device to UBA1, calls the next device to UBA2. Therefore the IO assignments in the table below do not necessarily match the names that UBE inventory performs.

Unibus Adapter Exerciser Configuration

Device

Interrupt
(BR)

Interrupt
Vector

Base
Address

UBE #1

Programmable

000510

770000

UBE #2

Programmable

000520

770020

UBE #3

Programmable

000530

770040

UBE #4

Programmable

000540

770060

UBE #5

Programmable

000550

770100

UBE #6

Programmable

000560

770120

UBE #7

Programmable

000570

770140

UBE #8

Programmable

000600

770160

UBE #9

Programmable

000610

770200

UBE #10

Programmable

000620

770220

UBE #11

Programmable

000630

770240

UBE #12

Programmable

000640

770260

UBE Interface Registers

These registers are visible to the KS10 processor

A summary of UBE interface registers is summarized below:

UBE Register Summary

IO Addr

Register
Name

Access

Register Description

Base + 0

UBEDB
UBEDB1

Byte (R/W)

UBE Data Buffer Register

Base + 2

UBECC
UBECC1

Byte (R/W)

UBE Cycle Count Register

Base + 4

UBEBA
UBEBA1

Byte (R/W)

UBE Buffer Address Register

Base + 6

UBECSR1
UBEC1A

Byte (R/W)

UBE Control/Status Register #1

Base + o10

UBECLR

Byte (R/W)

UBE Clear Error Register

Base + o16

UBECSR2 UBEC1B

Byte (R/W)

UBE Control/Status Register #2

770014

SIMGO

Byte (R/W)

Simultaneous GO Register

UBE Data Buffer Register (UBEDB)

The DB register is a data source or data sink for UBE NPR transfers.

This register may be accessed as a byte or a word.

UBE Data Buffer Register (UBEDB) – IO Offset 0

Bit(s)

Mnemonic

R/W

Description

15-0

DB

R/W

Data Buffer

This register is modified by writing to this register.

The DB register is cleared by issuing an IO Bridge Clear (UBACSR[INI] = '1').

UBE Cycle Count Register (UBECC)

The Cycle Count register is loaded with the two's complement of the number of NPR transfers to perform.

The Cycle Count register is incremented by one each time an 16-bit or 18-bit word NPR occurs. The Cycle register is incremented by two every time a 36-bit (Fast Transfer Mode) NPR operation occurs.

When the Cycle Count register is incremented to zero, the NPR operation is complete.

This register may be accessed as a byte or a word.

UBE Data Buffer Register (UBEDB) – IO Offset 2

Bit(s)

Mnemonic

R/W

Description

15-0

CC

R/W

Cycle Count

The Cycle Count register is modified by writing to this register and is incremented by one each time an 16-bit or 18-bit word NPR occurs. The Cycle register is also incremented by two every time a 36-bit (Fast Transfer Mode) NPR operation occurs.

The Cycle Count register is cleared by issuing an IO Bridge Clear (UBACSR[INI] = '1').

UBE Buffer Address Register (UBEBA)

The program loads the starting address (virtual address) of source memory (for writes) or the destination memory (for reads).

Each time a 16-bit or 18-bit word is transferred, the address is incremented by two. Each time a 36-bit word is transferred in Fast Transfer Mode (FTM), the address is incremented by four. In Fast Transfer Mode, the 2 LSBs must be zero, or the UBA will generate an IO Page Fault as described in the section that details IO Bridge Page Failures.

This register may be accessed as a byte or a word.

UBE Buffer Address Register (UBEBA) – IO Offset 4

Bit(s)

Mnemonic

R/W

Description

15-0

BA

R/W

Buffer Address

The Buffer Address register is modified by writing to this register and incremented by two each time a 16-bit or 18-bit word is transferred. The Buffer Address register is also incremented by four each time a 36-bit word is transferred in Fast Transfer Mode (FTM).

The BA register is cleared by issuing an IO Bridge Clear (UBACSR[INI] = '1').

UBE Control/Status Register #1 (UBECSR1)

The UBE Control/Status Register #1 is the primary register that is used to control the operation of the UBE.

This register may be accessed as a byte or a word.

UBE Control/Status Register #1 (UBECSR1) – IO Offset 6

Bit(s)

Mnemonic

R/W

Description

15

ERR

R

Error

The purpose of this bit is unknown.

14

UNK5

R/W

Unknown

The purpose of this bit is unknown.

The UNK5 register is asserted by writing a '1' to UNK5.

The UNK5 register is negated by:

  1. Writing a '0' to UNK5, or
  2. Asserting IO Bridge Clear (UBACSR[INI] = '1').

13

UNK4

R/W

Unknown

The purpose of this bit is unknown.

The UNK4 register is asserted by writing a '1' to UNK4.

The UNK4 register is negated by:

  1. Writing a '0' to UNK4, or
  2. Asserting IO Bridge Clear (UBACSR[INI] = '1').

12

UNK3

R/W

Unknown

The purpose of this bit is unknown.

The UNK3 register is asserted by writing a '1' to UNK3.

The UNK3 register is negated by:

  1. Writing a '0' to UNK3, or
  2. Asserting IO Bridge Clear (UBACSR[INI] = '1').

11

FTM

R/W

Fast Transfer Mode

In Fast Transfer Mode (FTM), even word transfers on Unibus are stored in the UBA and not immediately transferred to memory. When the odd word is accessed, the even word and odd word is transferred in a single 36-bit KS10 operation.

The FTM register is asserted by writing a '1' to FTM.

The FTM register is negated by:

  1. Writing a '0' to FTM, or
  2. Asserting IO Bridge Clear (UBACSR[INI] = '1').

10

XTCCO

R/W

Transfer Until Cycle Count Register Overflow

When this bit is asserted, the UBE performs NPR operations until the UBECC register increments to zero or overflow.

Note: I could be completely wrong about the meaning of this bit. DSUBA mentions a "XFER TIL CCOVF" bit but doesn't describe it's location. This looks like where it belongs.

XTCCO is cleared by issuing an IO Bridge Clear (UBACSR[INI] = '1').

The XTCCO register is asserted by writing a '1' to XTCCO.

The XTCCO register is negated by:

  1. Writing a '0' to XTCCO, or
  2. Asserting IO Bridge Clear (UBACSR[INI] = '1').

9

NPRO

R/W

NPR Out

When asserted, NPR operations are output from the UBE to KS10 memory. Otherwise, NPR operations are from KS10 memory to the UBE.

The NPRO register is asserted by writing a '1' to NPRO.

The NPRO register is negated by:

  1. Writing a '0' to NPRO, or
  2. Asserting IO Bridge Clear (UBACSR[INI] = '1').

8

BYTE

R/W

Byte Operation

When BYTE is asserted, NPR operations are byte operations. Otherwise, NPR operations are either 16-bit or 18-bit word operations.

The BYTE register is asserted by writing a '1' to BYTE.

The BYTE register is negated by:

  1. Writing a '0' to BYTE, or
  2. Asserting IO Bridge Clear (UBACSR[INI] = '1').

7

UNK2

R

Unknown

The purpose of this bit is unknown.

UNK2 is always read as zero.

6

UNK1

R/W

Unknown

The purpose of this bit is unknown.

The UNK1 register is asserted by writing a '1' to UNK1.

The UNK1 register is negated by:

  1. Writing a '0' to UNK1, or
  2. Asserting IO Bridge Clear (UBACSR[INI] = '1').

5

NPRS

R/W

Simulate NPR Cycles

When NPRS is asserted and GO is asserted (UBECSR1[GO] = '1'), the UBE will start an NPR operation.

The NPRS register is asserted by writing a '1' to NPRS.

The NPRS register is negated by:

  1. Writing a '0' to NPRS, or
  2. Asserting IO Bridge Clear (UBACSR[INI] = '1').

Note: I could be completely wrong about the meaning of this bit.

4

BR7

R/W

Interrupt Request 7

When BR7 is asserted and GO is asserted (UBECSR1[GO] = '1'), the UBE genterate a BR7 interrupt.

The BR7 register is asserted by writing a '1' to BR7.

The BR7 register is negated by:

  1. Writing a '0' to BR7, or
  2. Asserting IO Bridge Clear (UBACSR[INI] = '1').

3

BR6

R/W

Interrupt Request 6

When BR6 is asserted and GO is asserted (UBECSR1[GO] = '1'), the UBE genterate a BR6 interrupt.

The BR6 register is asserted by writing a '1' to BR6.

The BR6 register is negated by:

  1. Writing a '0' to BR6, or
  2. Asserting IO Bridge Clear (UBACSR[INI] = '1').

2

BR5

R/W

Interrupt Request 5

When BR5 is asserted and GO is asserted (UBECSR1[GO] = '1'), the UBE genterate a BR5 interrupt.

The BR5 register is asserted by writing a '1' to BR5.

The BR5 register is negated by:

  1. Writing a '0' to BR5, or
  2. Asserting IO Bridge Clear (UBACSR[INI] = '1').

1

BR4

R/W

Interrupt Request 4

When BR4 is asserted and GO is asserted (UBECSR1[GO] = '1'), the UBE genterate a BR4 interrupt.

The BR4 register is asserted by writing a '1' to BR4.

The BR4 register is negated by:

  1. Writing a '0' to BR4, or
  2. Asserting IO Bridge Clear (UBACSR[INI] = '1').

0

GO

R/W

GO

When GO is asserted and depending on the other bits in UBECSR1, the state machine will generate an interrupt or an NPR operation.

GO is always read as zero.

UBE Clear Error Register (UBECLR)

The UBECLR register is used to clear error status in UBECSR2 and to clear the state machine that generates NPR operations and interrupts.

This register may be accessed as a byte or a word.

UBE Clear Error Register (UBEBA) – IO Offset o10

Bit(s)

Mnemonic

R/W

Description

15-1

-

W

Reserved

Writes ignored.

Always read as zero.

0

CLR

W

Clear Error

Asserting CLR resets the state machine that generates Interrupts and NPR operations.

Negating CLR has no effect.

CLR is always read as zero.

UBE Control/Status Register #2 (UBECSR2)

The UBE Control/Status Register #2 is the primary register that is used to check the error status of the UBE.

This register may be accessed as a byte or a word.

UBE Control/Status Register #2 (UBECSR2) – IO Offset o16

Bit(s)

Mnemonic

R/W

Description

15

TIMEOUT

R

Timeout

The purpose of this bit is unknown and is not implemented.

Writes ignored.

Always read as zero.

14

BMD

R

Bad Memory Data

The purpose of this bit is unknown and is not implemented.

Writes ignored.

Always read as zero.

13

BPE

R

Bus Parity Error

The purpose of this bit is unknown and is not implemented.

Writes ignored.

Always read as zero.

12

NXD

R

Non Existent Device

The purpose of this bit is unknown and is not implemented.

Writes ignored.

Always read as zero.

11

USSE

R

Unibus No Interrupt Slave SSYNC Error

The purpose of this bit is unknown and is not implemented.

Writes ignored.

Always read as zero.

10

UNGG

R

Unibus Not Grant or Not One Grant

The purpose of this bit is unknown and is not implemented.

Writes ignored.

Always read as zero.

9

UWAL

R

Unibus Wrong A Lines

The purpose of this bit is unknown and is not implemented.

Writes ignored.

Always read as zero.

8

UNSE

R

Unibus No SSYN Error

The purpose of this bit is unknown and is not implemented.

Writes ignored.

Always read as zero.

7

UNST

R

Unibus No No SACK Timeout

The purpose of this bit is unknown and is not implemented.

Writes ignored.

Always read as zero.

6

UMLE

R

Unibus Max Late Error

The purpose of this bit is unknown and is not implemented.

Writes ignored.

Always read as zero.

5

UWGB

R

Unibus Wrong Grant Back

The purpose of this bit is unknown and is not implemented.

Writes ignored.

Always read as zero.

4

ACLO

R/W

AC Low

This bit indicates to the UBA that the power is off for this device. This is used to test UBASR[PWR].

The ACLO register is asserted by writing a '1' to ACLO.

The ACLO register is negated by:

  1. Writing a '0' to ACLO, or
  2. AssertingIO Bridge Clear (UBACSR[INI] = '1').

3

USED3

R/W

USED3

The purpose of this bit is unknown and is not implemented.

The USED3 register is asserted by writing a '1' to USED3.

The USED3 register is negated by:

  1. Writing a '0' to USED3, or
  2. Asserting IO Bridge Clear (UBACSR[INI] = '1').

2

USED2

R/W

USED2

The purpose of this bit is unknown and is not implemented.

The USED2 register is asserted by writing a '1' to USED2.

The USED2 register is negated by:

  1. Writing a '0' to USED2, or
  2. Asserting IO Bridge Clear (UBACSR[INI] = '1').

1

USED1

R/W

USED1

The purpose of this bit is unknown and is not implemented.

The USED1 register is asserted by writing a '1' to USED1.

The USED1 register is negated by:

  1. Writing a '0' to USED1, or
  2. Asserting IO Bridge Clear (UBACSR[INI] = '1').

0

USED0

R/W

USED0

The purpose of this bit is unknown and is not implemented.

The USED0 register is asserted by writing a '1' to USED0.

The USED0 register is negated by:

  1. Writing a '0' to USED0, or
  2. Asserting IO Bridge Clear (UBACSR[INI] = '1').

UBE Simultaneous GO Register (SIMGO)

This register is very different than all of the other UBE registers as it is affects every UBE. In other words, every UBE device decodes this address and has an identical copy of this register.

Writes to this register has the same effect as if every UBECSR1[GO] on every UBE was asserted simultaneously.

The software uses this feature for several tests:

  • The DSUBA software configures several UBE devices with different interrupt priorities, then asserts SIMGO to simultaneously cause each of the UBEs to generate an interrupt. The software verifies that the interrupts were handled in the proper order according to priority.
  • The DSUBA software configures a UBE to generate an NPR operation and configures another UBE to generate an interrupt operation. The software verifies that the NPR operation is handled before the interrupt operation.

This register may be accessed as a byte or a word.

UBE SIMGO Register (SIMGO) – IO Address 770014

Bit(s)

Mnemonic

R/W

Description

15-1

-

W

Reserved

Writes ignored.

Always read as zero.

0

SIMGO

W

Simultaneous GO

Asserting SIMGO has the same effect as if every UBECSR1[GO] on every UBE was asserted simultaneously.

Negating SIMGO has no effect.

SIMGO is always read as zero.

DSUBA Transcript

SMMON CMD - DSUBA

DECSYSTEM 2020 UNIBUS ADAPTER EXERCISER  [ DSUBA ]
VERSION 0.4, SV=0.3, CPU#=2020, MCV=130, MCO=470, HO=0, KASW=003740 000000

TTY SWITCH CONTROL ? - 0,S OR Y <CR> - 0<CR>
SWITCHES = 000000 000000

MEMORY MAP =
FROM     TO          SIZE/K
00000000 03777777       1024


WHICH UNIBUS ADAPTER? (1,3,4):4<CR>

UBE     BASE ADDRESS    VECTOR
______________________________
01      4770000         0510
02      4770020         0520
03      4770040         0530
04      4770060         0540

END PASS 1.

UBE Status

The UBE is fully debugged and stable.

The diagnostic status is summarized below:

                           DIAGNOSTIC                            Result
---------------------------------------------------------------- ------
DSUBAC0 DECSYSTEM 2020 UNIBUS ADAPTER EXERCISER  . . . . . . . . Pass
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