Massbus Disk Controller (RP) - KS10FPGA/KS10FPGA GitHub Wiki
This Massbus Disk Controller provides an Massbus interface to 8 Disk Drives. A block diagram of the RH11 Massbus Interface and the Massbus Disk Controller is illustrated below:
Unlike a genuine DEC Massbus-based system whereas each disk drive has an independent Massbus interface and has independent rotating storage media; the implementation in the KS10 FPGA shares the Massbus interface and uses a single modern inexpensive solid state Secure Digital High Capacity (SDHC) as the storage media for all 8 disk drives.
Although the term "Massbus" is used above, the Massbus implementation in the KS10 FPGA barely resembles a DEC Massbus implementation although it serves exactly the same purpose. The Massbus interface differs in the following areas:
- Data paths in the KS10 FPGA are not tristate or bi-directional and are 36-bits wide. There is a separate data path for data going to the Massbus device and for data coming from the Massbus device.
- The interface is fully synchronous and operates at the CPU clock speed. It is much faster than Massbus.
- Massbus register addressing is retained.
- Control bus and data bus parity is not implemented.
While the picture above shows RP06 drives, the disk controller is fully parameterized to support the implementation of varying sized (and geometry) disk drives and can control any type of supported disk drives. Having said that, only the RP06 has received any testing at all.
The Massbus Disk Controller can be conditionally compiled to support the following disk drive types:
- RP04
- RP05
- RP06
- RP07
- RM03
- RM05
- RM80
Note: the RMxx series disks will probably require some design changes to fully support and I'm only aware of diagnostics for the RP06 and the RM03.
In the block diagram above, the Massbus Controller Interface provides the interface to the Massbus. The interface selects one of the disk drives and it multiplexes status responses and data from the selected disk drive back onto the Massbus.
Each disk drive simulates rotational latency and seek timing. Each disk drive maintains a notion of the current ‘head position’ and will simulate a delay that would appropriate for a disk drive as the heads are moved to different tracks or sectors based on the command inputs. This can be accomplished with varying degrees of precision: it goes without saying that the Secure Digital (SD) disk chip has zero seek delay and zero rotational latency. This is done strictly for compatibility with the original disk systems. Some experimentation will be required to determine if this simulation fidelity is required, or not. When a command is issued, the disk drive determines if the command requires access to the SD Card storage media. If access to the SD Card is required, the disk drive calculates a 32-bit Linear Sector Address for the SD Card based on the Cylinder, Head, and Sector. Lastly the disk issues a request to access the SD Card after the seek and search timing delays have expired.
The Disk Completion Monitor arbitrates between the various requests to access the SD Card.
The SD Card Interface State Machine configures the SD Card and performs read, write, and write-check operations.
These disk geometries are summarized as follows:
Common PDP-10 Disk Parameters |
||||||
Parameter |
RM02/RM03 |
RM05 |
RM80 |
RP04/RP05 |
RP06 |
RP07 |
36-bit Words per Sector |
128 |
128 |
128 |
128 |
128 |
128 |
Sector per Track |
30 |
30 |
30 |
20 |
20 |
43 |
Tracks per Cylinder |
5 |
19 |
14 |
19 |
19 |
32 |
Cylinders per Pack |
823 |
823 |
559 |
411 |
815 |
630 |
PDP10 Disk Size (words) |
15,801,600 |
60,046,080 |
30,051,840 |
19,991,040 |
39,641,600 |
110,960,640 |
SIMH Disk Size (bytes) |
126,412,800 |
480,368,640 |
240,414,720 |
159,928,320 |
317,132,800 |
887,685,120 |
See this discussion regarding TOPS-10 and Tops-20 support of the RP07.
The disk type is altered by modifying the 'condition compiles' in the Verilog code. Right now, only the RP06 has received any testing at all. The other disk types will be tested at a later time.
The SD Card is actually a pretty good match to the Massbus disk drives of the day. Compatibility issues between the disk drives and SD Card storage will be discussed in the following sections.
As background, the DEC PDP-10 Massbus disks all used 128 36-bit words per sector.
The SD Card, by default, supports a 512-byte sector size. The mapping between the two different types of storage media is important to understand.
As with SIMH, the KS10 FPGA stores the 36-bit data in an 64-bit (8-byte) data word. It is a simple calculation to show that a sector of PDP-10 disk storage requires exactly 1024 bytes of SD Card storage. Therefore each sector of the Massbus disk requires exactly two sectors of SD storage.
Thus the mapping between PDP-10 disk sectors and SD Card sectors is straight forward.
Massbus disks used Cylinder, Track, and Sector addressing while the SD Card uses a 32-bit Linear Sector Address.
The Massbus Disk controller in the FPGA simply calculates the Linear Sector Address based on the Cylinder, Track, and Sector address using the following equation:
Linear Sector Address = ((((C * NH) + T) * NS) + S) * 2
Where:
C = Requested Cylinder from the Desired Cylinder (RPDC) Register
T = Track/Surface/Head from the Disk Address (RPDA) Register
S = Sector from the Disk Address (RPDA) Register
NH = Number of Heads (RP06=19)
NS = Number of Sectors per Cylinder (RP06=20)
Note, in the case of the RP06, the constant NH is 19 and the constant NS is 20. The multiplication by these two constants is troublesome but not impossible. The KS10 FPGA implements this algorithm using a state machine and repeated additions. Because the Massbus Disk Controller simulates disk motion, there are a lot of clock cycles available to perform repeated additions to implement this equation.
The linear sector addressing used by the KS10 FPGA exactly matches the mapping
used by SIMH, although SIMH uses byte offsets (off_t) applied to
the lseek() function.
The RP06 disk drive spins at 3600 RPM (or 60 rotations per second).
In 18-bit mode, a track of data contains 20 sectors. Each sector contains 672 bytes of header plus data. Therefore the data transfer rate of the RP06 in 18-bit mode can be calculated to be 806,400 bytes per second.
In 16-bit mode, a track of data contains 22 sectors. Each sector contains 608 bytes of header plus data. Therefore the data transfer rate of the RP06 in 16-bit mode is calculated to be 802,560 bytes per second.
These calculations are consistent with the advertised data transfer rate of 806,000 bytes per second that is documented in the Memorex 677 Disc Storage Device Technical Manual in Section 1.1.1.
The SD Card interface is clocked at a rate that is relatively consistent with the transfer rate of the disk drive.
The SD Card has no inherent seek time (head motion) or search time (rotational latency). These delays are emulated (added) by the FPGA firmware.
The Massbus Disk Controller can be conditionally compiled in one of two modes: "fast and loose" or "slow but accurate". The "slow but accurate" mode is required to pass many of the DSRPA diagnostics. In this mode, the FPGA simulates head motion (seek times), disk rotation (search times), and data transfer rates. The "fast and loose" mode just uses the SD Card with very little external delays. That seems to be good enough for everything but everything except the diagnostics and is consistent with the SIMH implementation.
A Massbus disk drive always reads full sectors. On writes, a Massbus disk drive may be presented a partial sector of data. In that case, the remainder of the sector is filled with zero. The FPGA firmware fills the SD Card with zeros on partial writes as appropriate.
As an example, the RP06 has 5 platters. Each platter has 4 heads - which is a bit unusual in that each surface of the platter has two heads. One of the heads is a dedicated servo track therefore there are only 19 tracks available for data storage.
The RP06 has 20 sectors per track in an 18-bit mode and has 22 sectors per track in a 16-bit mode. Currently, the KS10 FPGA can only read/write data in an 18-bit mode; the 16-bit mode is only partly implemented as required for the DSRPA diagnostics.
The RP06 has 815 cylinders, 19 tracks per cylinder, and 20 sectors per track. The last 5 cylinders are dedicated to maintenance and are not used by the operating systems.
Massbus Disk Addressing
Each of the individual disk drives maintains its own state. In this context, that device state includes everything that would normally be associated with the physical disk drive. That device state includes the following registers:
RPxx Device Registers |
|||||
Unibus Address |
Massbus Address |
RP Register Name |
RM Register Name |
R/W |
Register Description |
776700 |
0 |
R/W |
Control and Status Register #1 |
||
776702 |
- |
R/W |
Word Count Register |
||
776704 |
- |
R/W |
Bus Address Register |
||
776706 |
5 |
R/W |
Disk Address Register |
||
776710 |
- |
R/W |
Control and Status Register #2 |
||
776712 |
1 |
R |
Drive Status Register |
||
776714 |
2 |
R/W |
Error Register #1 Register |
||
776716 |
4 |
R/W |
Attention Summary Register |
||
776720 |
7 |
R |
Look Ahead Register |
||
776724 |
3 |
R/W |
Maintenance Register |
||
776726 |
6 |
R |
Drive Type Register |
||
776730 |
10 |
R |
Serial Number Register |
||
776732 |
11 |
R/W |
Offset Register |
||
776734 |
12 |
R/W |
Desired Cylinder Register |
||
776736 |
13 |
- |
R |
Current Cylinder |
|
- |
RMHR |
R |
Holding Register |
||
776740 |
14 |
- |
R/W |
Error Register #2 |
|
- |
RMMR2 |
R |
Maintenance Register #2 |
||
776742 |
15 |
- |
R/W |
Error Register #3 |
|
- |
RMER2 |
R/W |
Error Register #2 |
||
776744 |
16 |
R |
ECC Position Register |
||
776746 |
17 |
R |
ECC Pattern Register |
||
Some of the bits in the RPCS1 Register are implemented in the RH11 Controller and some bits are implemented in the RPxx Device.
RPxx Control and Status Register #1 (RPCS1)
RP Control and Status Register #1 (RPCS1) – IO Address 776700 |
||||
Bit(s) |
Mnemonic |
R/W |
Description |
|
15 |
SC |
R |
See RH controller |
|
14 |
TRE |
R/W |
See RH controller |
|
13 |
CPE |
R |
See RH controller |
|
12 |
0 |
R |
See RH controller |
|
11 |
DVA |
R |
Drive available Always read as '1'. |
|
10 |
PSEL |
R/W |
See RH controller |
|
9 |
A17 |
R/W |
See RH controller |
|
8 |
A16 |
R/W |
See RH controller |
|
7 |
RDY |
R |
See RH controller |
|
6 |
IE |
R/W |
See RH controller |
|
5-1 |
FUN |
R/W |
Controller Function FUN is only modified by writing to this field. FUN is NOT reset by either:
|
|
Code |
Description |
|||
00 |
No operation |
|||
01 |
Unload |
|||
02 |
Seek |
|||
03 |
Recalibrate |
|||
04 |
Drive Clear |
|||
05 |
Release |
|||
06 |
Offset |
|||
07 |
Return to center |
|||
10 |
Read-in preset |
|||
11 |
Pack acknowledge |
|||
12-13 |
Illegal function(s) |
|||
14 |
Search |
|||
15-23 |
Illegal function(s) |
|||
24 |
Write check data |
|||
25 |
Write check header and data |
|||
26-27 |
Illegal function(s) |
|||
30 |
Write data |
|||
31 |
Write header and data |
|||
32-33 |
Illegal function(s) |
|||
34 |
Read data |
|||
35 |
Read header and data |
|||
36-37 |
Illegal function(s) |
|||
0 |
GO |
R/W |
Execute function specified in FUN field. Set by writing a 1 with Parity Test (RHCS2[PAT]) negated. Cleared when the command completes. This register is NOT reset by either:
Note: The unit will not execute a command with incorrect parity. |
|
This register addresses the sector and track of the selected unit.
The Sector Address is used by the "search command" - either implied or otherwise.
The Track Address selects the disk head.
The disk address is incremented after the sector has been transferred to the controller.
The address increment is accomplished as follows:
if (sector == last_sector)
begin
sector <= 0;
if (track == last_track)
begin
track <= 0
cylinder <= cylinder + 1
end
else
track <= track + 1
end
else
sector <= sector + 1
end
RPxx Disk Address Register (RPDA)
RP Disk Address Register (RPDA) – IO Address 776706 |
|||
Bit(s) |
Mnemonic |
R/W |
Description |
15-8 |
TA |
R/W |
Track address. Altered by writing. Cleared by Read-in Preset command. This register is NOT reset by either:
Note: The track address must be valid for the type of disk. The number bits in this register field that are actually implemented will depend on the disk drive parameters. |
7-0 |
SA |
R/W |
Sector address. Altered by writing. Cleared by Read-in Preset command. This register is NOT reset by either:
Note: The sector address must be valid for the type of disk. The number bits in this register field that are actually implemented will depend on the disk drive parameters. |
This register reports the status of the disk drive
RPxx Drive Status Register (RPDS)
RP Drive Status Register (RPDS) – IO Address 776712 |
|||
Bit(s) |
Mnemonic |
R/W |
Description |
15 |
ATA |
R |
Attention Active ATA is asserted under the following conditions:
ATA is negated under the following conditions:
|
14 |
ERR |
R |
Composite Error ERR is asserted if any bits in RPER1, RPER2, or RPER3 are set. This bit is combinationally derived from those registers – clearing that bit in that register will negate ERR. When ERR is asserted, the only command that is accepted is the Drive Clear (RPCS1[FUN] = 4) command. |
13 |
PIP |
R |
Positioning in progress PIP is asserted when of the following “Positioning Commands” is active:
PIP is negated when the positioning command completes. PIP is not set during an implied seek or a mid-transfer seek. Note: The RP05/RP06 Control Logic Maintenance Manual (EK-RP056-MM-01) Table 2-1 says that PIP is asserted during a search operation. This is incorrect. The RP06 will fail the DSRPA diagnostics TEST-276 if PIP is set during a search operation. |
12 |
MOL |
R |
Media On-line MOL is asserted when an SD Card is inserted in the SD socket and has been initialized successfully. MOL is negated when the SD Card is removed from the SD Socket. |
11 |
WRL |
R |
Write Lock On a 'real' disk drive, this would be controlled by a switch on the disk drive. In the KS10 FPGA, this is controlled by the RH11 Console Control Register which allows the operator to write protect the disk drive. |
10 |
LST |
R |
Last Sector Transferred LST is asserted when the last addressable sector has been read or written. LST is negated when RPDA is written. |
9 |
PGM |
R |
Programmable PGM is always read as zero. |
8 |
DPR |
R |
Drive Present On a 'real' disk drive, this would be controlled by the disk drive. In the KS10 FPGA, this is controlled by the RH11 Console Control Register which allows the operator to take disk drive offline. |
7 |
DRY |
R |
Drive Ready DRY is asserted at the completion of every command. DRY is negated at the start of every command. |
6 |
VV |
R |
Volume Valid VV is asserted under the following conditions:
VV is negated when the device transitions from off-line (RPDS[MOL] = '0') to online (RPDS[MOL] = '1'). This normally occurs when the SD card is inserted into the SD slot. VV is NOT cleared by Cleared by:
Notes:
|
5 |
DE1 |
R |
Difference Equals 1 Always read as zero. DE1 is a signal from RP04 disk which indicates head load sequence status. DE1 is not implemented by the RP05/RP06 disk and is ignored by the diagnostics. See Note 2 on M7789/MB1. On the schematic, this pin has pulldown resistor. |
4 |
DL64 |
R |
Difference less than 64 Always read as zero. DL64 is a signal from RP04 disk which indicates head load sequence status. DL64 is not implemented by the RP05/RP06 disk and is ignored by the diagnostics. See Note 2 on M7789/MB1. On the schematic, this pin has pulldown resistor. |
3 |
GRV |
R |
Go Reverse Always read as zero. GRV is a signal from RP04 disk which indicates head load sequence status. GRV is not implemented by the RP05/RP06 disk and is ignored by the diagnostics. See Note 2 on M7789/MB1. On the schematic, this pin has pulldown resistor. |
2 |
DIGB |
R |
Drive to Inner Guard Buffer Always read as zero. DIGB is a signal from RP04 disk which indicates head load sequence status. DIGB is not implemented by the RP05/RP06 disk and is ignored by the diagnostics. See Note 2 on M7789/MB1. On the schematic, this pin has pulldown resistor. |
1 |
DF20 |
R |
Drive Forward 20 inches/sec Always read as zero. DF20 is a signal from RP04 disk which indicates head load sequence status. DF20 is not implemented by the RP05/RP06 disk and is ignored by the diagnostics. See Note 2 on M7789/MB1. On the schematic, this pin has pulldown resistor. |
0 |
DF5 |
R |
Drive Forward 5 inches/sec Always read as zero. DF5 is a signal from RP04 disk which indicates head load sequence status. DF5 is not implemented by the RP05/RP06 disk and is ignored by the diagnostics. See Note 2 on M7789/MB1. On the schematic, this pin has pulldown resistor. |
This register contains the error status of the addressed drive.
RPxx Error Register #1 (RPER1)
RP Error Register #1 (RPER1) – IO Address 776714 |
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Bit(s) |
Mnemonic |
R/W |
Description |
15 |
DCK |
R/W |
Data Check DCK is implemented only as necessary to pass certain diagnostic tests. DCK is asserted under the following conditions:
DCK is negated under the following conditions:
|
14 |
UNS |
R/W |
Unsafe Not implemented. UNS is asserted by writing a '1' to DCK. UNS is negated under the following conditions:
|
13 |
OPI |
R/W |
Operation Incomplete OPI is implemented only as necessary to pass certain diagnostic tests. OPI is asserted under the following conditions:
OPI is negated under the following conditions:
|
12 |
DTE |
R/W |
Drive Timing Error DTE is implemented only as necessary to pass certain diagnostic tests. DTE is asserted under the following conditions:
DTE is negated under the following conditions:
|
11 |
WLE |
R/W |
Write Lock Error WLE is asserted by executing a Write Command on a write protected drive. WLE is negated under the following conditions:
|
10 |
IAE |
R/W |
Invalid Address Error IAE is asserted when an invalid cylinder, sector, or track is selected and any of the following commands is executed:
OPI is negated under the following conditions:
|
9 |
AOE |
R/W |
Address Overflow Error AOE is implemented only as necessary to pass certain diagnostic tests. AOE is asserted under the following conditions:
AOE is negated under the following conditions:
|
8 |
HCRC |
R/W |
Header CRC Error HCRC is implemented only as necessary to pass certain diagnostic tests. HCRC is asserted under the following conditions:
AOE is negated under the following conditions:
|
7 |
HCE |
R/W |
Header Compare Error HCE is not implemented. HCE is asserted by writing a '1' to HCE. HCE is negated under the following conditions:
|
5 |
WCF |
R/W |
Write Clock Failure WCF is not implemented. WCF is asserted by writing a '1' to WCF. WCF is negated under the following conditions:
|
4 |
FER |
R/W |
Format Error FER is not implemented. FER is asserted by writing a '1' to FER. FER is negated under the following conditions:
|
3 |
PAR |
R/W |
Parity Error PAR is implemented only as necessary to pass certain diagnostic tests. Normal parity is not implemented. PAR is asserted under the following conditions:
PAR is negated under the following conditions:
|
2 |
RMR |
R/W |
Register Modification Refused RMR is asserted under the following conditions:
RMR is negated under the following conditions:
|
1 |
ILR |
R/W |
Illegal Register ILR should probably be asserted if a Massbus address greater than 017 (or an address past RPEC2) is accessed. ILR isn't implemented because it isn't tested. ILR is tested by the MT controller. ILR is asserted by writing a '1' to ILR. ILR is negated under the following conditions:
|
0 |
ILF |
R/W |
Illegal Function ILF is asserted under the following conditions:
ILF is negated under the following conditions:
|
The Attention Summary Pseudo Register allows the program to examine or modify the status of all disk drives in a single operation.
RPxx Attention Summary Register (RPAS
RP Attention Summary (RPAS) – IO Address 776716 |
|||
Bit(s) |
Mnemonic |
R/W |
Description |
15-8 |
- |
R |
Writes ignored. Always read as zero. |
7 |
ATA7 |
R/W |
Attention Active on Disk 7 ATA7 reflects value of Disk 7's RPDS[ATA]. ATA7 is negated by writing 1 to Disk 7's RPDS[ATA]. |
6 |
ATA6 |
R/W |
Attention Active on Disk 6 ATA6 reflects value of Disk 6's RPDS[ATA]. ATA6 is negated by writing 1 to Disk 6's RPDS[ATA]. |
5 |
ATA5 |
R/W |
Attention Active on Disk 5 ATA5 reflects value of Disk 5's RPDS[ATA]. ATA5 is negated by writing 1 to Disk 5's RPDS[ATA]. |
4 |
ATA4 |
R/W |
Attention Active on Disk 4 ATA4 reflects value of Disk 4's RPDS[ATA]. ATA4 is negated by writing 1 to Disk 4's RPDS[ATA]. |
3 |
ATA3 |
R/W |
Attention Active on Disk 3 ATA3 reflects value of Disk 3's RPDS[ATA]. ATA3 is negated by writing 1 to Disk 3's RPDS[ATA]. |
2 |
ATA2 |
R/W |
Attention Active on Disk 2 ATA2 reflects value of Disk 2's RPDS[ATA]. ATA2 is negated by writing 1 to Disk 2's RPDS[ATA]. |
1 |
ATA1 |
R/W |
Attention Active on Disk 1 ATA1 reflects value of Disk 1's RPDS[ATA]. ATA1 is negated by writing 1 to Disk 1's RPDS[ATA]. |
0 |
ATA0 |
R/W |
Attention Active on Disk 0 ATA0 reflects value of Disk 0's RPDS[ATA]. ATA0 is negated by writing 1 to Disk 0's RPDS[ATA]. |
This register would normally report the sector “under the head”. Highly optimized software could look at the current sector and optimally access data based on the actual sector position. This is not really necessary for Secure Digital (SDHC) media as it has no rotational latency.
HOWEVER –
Some DSRPA diagnostics expect that the bit fields in the RPLA register change in a sensible manner - i.e., the disk rotates at 3600 RPM and the sectors change accordingly. Also some diagnostics expect that when a search command completes, the contents of the RPLA register are consistent with the sector specified in the RPDA register.
The RPXX has special Diagnostic Mode hardware that allows the sector addressing to be tested via the Maintenance Mode Register (RPMR) and the Look Ahead Register (RPLA). This is enabled when the unit is in Diagnostic Mode (RPMR[DMD] asserted).
In 18-bit mode (RPMR[FMT22] negated), there are 20 sectors per track. There are 672 bytes per sector and therefore 13440 bytes per track. Of the 672 bytes of data per sector, 576 bytes are payload and 96 bytes are pre-header, header, header gap, ECC, data gap, and tolerance gap.
In 16-bit mode, (RPMR[FMT22] asserted), there are 22 sectors per track. There are 608 bytes per sector and therefore 13376 bytes per track. Of the 608 bytes of data per sector, 512 bytes are payload and 96 bytes are pre-header, header, header gap, ECC, data gap, and tolerance gap.
The sector byte counter can be reset by simulating an index pulse by setting then clearing the Diagnostic Index Pulse bit of the Maintenance Register (RPMR[DIND]). Thereafter, the sector byte counter can be incremented by bit-banging the Diagnostic Sector Clock (RPMR[DSCK]) bit. The result can be observed via the Look Ahead Register.
The Look Ahead Extension (RPLA[LAE]) field is incremented to 1 on the 127th clock pulse, incremented to 2 on the 255th clock pulse, and incremented to 3 on the 511th clock pulse. In 18-bit mode (RPMR[FMT22] negated), the Look Ahead Extension field is incremented back to 0 and the Look Ahead Sector (RLPA[LAS]) field is incremented on the 672nd clock pulse. In 16-bit mode, (RPMR[FMT22] asserted), the Look Ahead Extension field is incremented back to 0 and the Look Ahead Sector field is incremented on the 609th clock pulse.
RPxx Look Ahead Register (RPLA)
RP Look Ahead (RPLA) – IO Address 776720 |
|||||
Bit(s) |
Mnemonic |
R/W |
Description |
||
15-12 |
- |
R |
Writes ignored. Always read as zero. |
||
11-6 |
LAS |
R |
Look Ahead Sector LAS is implemented only as necessary to pass certain diagnostic tests. In Diagnostic Mode (RPMR[DMD] asserted), LAS indicates the Sector ‘under the head’ as follows:
Writes ignored. |
||
5-4 |
LAE |
R |
Look Ahead Extension Look Ahead Extension is also only implemented as necessary to pass certain diagnostic tests. |
||
BIT |
BIT |
Description |
|||
0 |
0 |
First quarter This is asserted during the sector clocks 0 thru 127. |
|||
0 |
1 |
Second quarter This is asserted during the sector clocks 128 thru 255. |
|||
1 |
0 |
Third quarter This is asserted during the sector clocks 256 thru 511. |
|||
1 |
1 |
Fourth quarter This is asserted during the sector clocks above 512. |
|||
3-0 |
- |
R |
Writes ignored. Always read as zero. |
||
The maintenance register is implemented as much as is required to pass diagnostic tests.
RPxx Maintenance Register (RPMR)
RP Maintenance Register (RPMR) – IO Address 776724 |
|||
Bit(s) |
Mnemonic |
R/W |
Description |
15-10 |
- |
R |
The M7774 schematic (Sheet RG2) implies that these bits were used by the RP04. I cannot confirm that. They are tied to GND on the RP06 backplane. Writes ignored. Always read as zero. |
9 |
SBD |
R |
Sync Byte Detected SBD is implemented in Diagnostic Mode only and is asserted when Sync Bytes are detected in the Disk Header. This implementation is only required to pass certain diagnostics. Writes ignored. Sync Bytes separate various fields in the disk header. Note: On a real RPxx disk, after the sector pulse, the data is stored on the disk as follows:
|
8 |
ZD |
R |
Zero detect ZD is implemented in Diagnostic Mode only and is asserted if the ECC is zero after reading the ECC field. This implementation is only required to pass certain diagnostics. Read only. Writes ignored. |
7 |
DFE |
R |
Data Field Envelope DFE is implemented in Diagnostic Mode only and is asserted when the Data Field of the sector is under the disk head. This field of the disk stores 256 words of data. This corresponds to 4608 bits in 16-bit mode or 4096 bits in 16-bit mode. DFE is asserted on the bits (set by RPMR[DCLK]) of the sector as follows:
Read only. Writes ignored. Note: The EK-RP056-MM-01 (Dec 1975) Maintenance Manual documents this bit in the wrong position of the RPMR. See MP-00086 Schematics (M7774/RG2) and DSRPA diagnostic. |
6 |
ECE |
R |
Error Correction Envelope ECE is asserted when the ECC Field or the sector is under the disk head. This field of the disk stores 2x 16-bit words of data or a 32 bits. DFE is asserted on the bits (set by RPMR[DCLK]) of the sector as follows:
Read only. Writes ignored. Note: The EK-RP056-MM-01 (Dec 1975) Maintenance Manual documents this bit in the wrong position of the RPMR. See MP-00086 Schematics (M7774/RG2) and DSRPA diagnostic. |
5 |
DWRD |
R/W |
Diagnostic Write Data In Diagnostic Mode (RPMR[DMD] asserted) and during a Write Data Command or Write Header Command the bits that would have been written to the disk can be read serially from this bit. This includes the sector header (if applicable), data fields, ECC fields, and data gap. These bits are clocked by the falling edge of the Diagnostic Data Clock (RPMR[DCLK]). Read only. Writes ignored. |
4 |
DRDD |
R/W |
Diagnostic Read Data In Diagnostic Mode (RPMR[DMD] asserted) and during a Read Command, Read Header Command, Write Check Command, or Write Check Header Command, the bits that are read by this port are handled by the controller as if they had been read by the disk drive. This includes the sector header (if applicable), data fields, ECC fields, and data gap. These bits are clocked by the falling edge of the Diagnostic Data Clock (RPMR[DCLK]). Reading this bit returns the last value that was written. When RPMR[DMD] is negated, this signal is held in reset. Read only. Writes ignored. |
3 |
DSCK |
R/W |
Diagnostic Sector Clock In Normal Mode (RPMR[DMD] = '0'), writes are ignored and DSC is read as zero. In this mode on a real RP06, the sector clock is used to read bytes into the data shift register. The KS10 FPGA implementation using a SD Card does not require a sector clock so this is not implemented. In Diagnostic Mode (RPMR[DMD] = '1'), DSC becomes read/write. In this mode, writing a '1' to DSCK generates a sector clock. The Sector Counter (and Sector Extension Counter) is incremented once per byte of data and may be observed by reading the RPLA register contents. See the RPLA register description. This allows the drive electronics to be tested without a functioning disk drive but is only implemented as required to pass certain diagnostic tests. |
2 |
DIND |
R/W |
Diagnostic Index Pulse In Normal Mode (RPMR[DMD] = '0'), writes are ignored and DIND is read as zero. In this mode on a real RP06,the Sector Pulse is read optically from the disk media and is asserted immediately before the first sector on the cylinder. The KS10 FPGA implementation using an SD Card does not require a Index Pulse so this is not implemented. In Diagnostic Mode (RPMR[DMD] = '1'), DIND becomes read/write. In this mode, the Sector Pulse can be simulated by writing to DIND. This resets the Sector Counter (see RPLA register). This allows the drive electronics to be tested without a functioning disk drive but is only implemented as required to pass certain diagnostic tests. |
1 |
DCLK |
R/W |
Diagnostic Data Clock In Normal Mode (RPMR[DMD] = '0'), writes are ignored and DCLK is read as zero. In this mode on a real RP06, the Data Clock is encoded with the Data and is stored on the rotating media. The Data Clock is recovered by the drive electronics as the signal from the read head is read from the disk drive. The KS10 FPGA implementation using an SD Card does not require a Data Clock so this is not implemented. In Diagnostic Mode (RPMR[DMD] = '1'), DCLK becomes read/write. In this mode, the Data Clock can be simulated by writing to DCLK. Each rising edge of the DCLK clocks one bit of data as if the data was read from the disk drive. This allows the drive electronics to be tested without a functioning disk drive but is only implemented as required to pass certain diagnostic tests. |
0 |
DMD |
R/W |
Diagnostic Mode Asserting DMD configures the disk drive into Diagnostic Mode. |
This register indicates the type of disk drive or tape drive that is connected to the controller.
RPxx Drive Type Register (RPDT)
RP Drive Type Register (RPDT) – IO Address 776726 |
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Bit(s) |
Mnemonic |
R/W |
Drive |
Register Contents |
15-14 |
- |
R |
All |
Always zero. |
13 |
MOH |
R |
All |
Always one. Indicates a 'moving head' disk drive. |
12 |
- |
R |
All |
Always zero. |
11 |
DRQ |
R |
All |
Always one. This is not a 'dual port' disk drive. |
10-8 |
- |
R |
All |
Always zero. |
7-0 |
DT |
R |
RP04 |
020. RPDT reports 020020 |
RP05 |
021. RPDT reports 020021 |
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RP06 |
022. RPDT reports 020022 |
|||
RM03 |
024. RPDT reports 020024 |
|||
RM80 |
026. RPDT reports 020026 |
|||
RM05 |
027. RPDT reports 020027 |
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RP07 |
042. RPDT reports 020042 |
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The RPSN register reports the Serial Number of the disk drive. The Serial Number is hardwired to the disk drive number. The values implemented in the FPGA are the same values that SIMH uses.
RPxx Serial Number Register (RPSN)
RP Serial Number Register (RPSN) – IO Address 776730 |
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Bit(s) |
Mnemonic |
R/W |
Drive |
Register Contents |
15-0 |
SN |
R |
0 |
000021 |
1 |
000022 |
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2 |
000023 |
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3 |
000024 |
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4 |
000025 |
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5 |
000026 |
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6 |
000027 |
|||
7 |
000030 |
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An RPxx drive has the ability to offset its heads off of the track centerline in either direction. This would have been useful to read data of a disk drive where the head position was uncalibrated or where the disk had become damaged.
RPxx Offset Register (RPOF)
RP Offset Register (RPOF) – IO Address 776732 |
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Bit(s) |
Mnemonic |
R/W |
Description |
15 |
SCG |
R |
Sign Change Not implemented. A real disk would use this to verify head alignment. SCG is masked/ignored by diagnostics. Writes ignored. Always read as zero. Note: The document “RP04 Moving Head Disk Subsystem Maintenance Manual”(DEC-11-HRJPA-B-D) says that SCG is read/write while the schematic shows it as read-only. |
14-13 |
- |
R |
Writes ignored. Always read as zero. |
12 |
FMT22 |
R/W |
Format FMT22 is implemented only as necessary to pass certain diagnostic tests. In Diagnostic Mode (RPMR[DMD] = '1'), FMT22 controls whether the disk is configured for 16-bit or 18-bit operation. When FMT22 is negated, the disk drive and controller is configured for 18-bit operation. When FMT22 is asserted, the disk drive and controller is configured for 16-bit operation. In this implementation and regardless of the settings when not in Diagnostic Mode, the disk drive always operates in 18-bit mode. FMT22 is asserted by writing a '1 to FMT22. FMT22 is negated by:
|
11 |
ECI |
R/W |
Error Correction Inhibit ECI is implemented only as necessary to pass certain diagnostic tests. In Diagnostic Mode (RPMR[DMD] asserted), ECI inhibits the Error Correction when a ECC error is detected. ECI is asserted by writing a '1 to ECI. ECI is negated by:
|
10 |
HCI |
R/W |
Header Compare Inhibit HCI is implemented only as necessary to pass certain diagnostic tests. In Diagnostic Mode (RPMR[DMD] asserted), HCI prevents reporting the header CRC errors. See RPER1[HCRC]. HCI is asserted by writing a '1 to HCI. HCI is negated by:
|
9-8 |
- |
R |
Writes ignored. Always read as zero. |
7 |
OFD |
R/W |
Head offset Direction OFD is implemented only as necessary to pass certain diagnostic tests. OFD does nothing. Normally this would control the direction that the head is offset from the center of the track. OFD is asserted by writing a '1 to OFD. OFD is negated by:
|
6-0 |
OFS |
R/W |
Head offset in 25 micro-inch increments OFS is implemented only as necessary to pass certain diagnostic tests. OFS does nothing. Normally this would control the distance that the head is offset from the center of the track. OFS is asserted by writing a '1 to OFS. OFS is negated by:
|
A seek operation, implied or otherwise, seeks to the cylinder that is specified in this register.
RPxx Desired Cylinder Register (RPDC)
RP Desired Cylinder (RPDC) – IO Address 776734 |
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Bit(s) |
Mnemonic |
R/W |
Description |
15-10 |
- |
R |
Writes ignored. Always read as zero. |
9-0 |
DCA |
R/W |
Desired Cylinder DCA is modified by writing. DCA Incremented following a read/write of the last sector of the last track of the cylinder. Cleared by:
DCA is NOT reset by either asserting IO Bridge Clear (UBACSR[INI]), or asserting Controller Clear (RHCS1[CLR]). |
This register contains the current head position.
RPxx Current Cylinder Register (RPCC)
RP Desired Cylinder (RPCC) – IO Address 776736 |
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Bit(s) |
Mnemonic |
R/W |
Description |
15-10 |
- |
R |
Writes ignored. Always read as zero. |
9-0 |
CCA |
R |
Current Cylinder Address
The Current Cylinder Address (CCA) is updated with the contents of the Desired Cylinder Address (DCA) under the following conditions:
CCA is cleared by a Recalibrate Command. Note: In Diagnostic Mode (RPMR[DMD] = '1'), everything described above still occurs; however, the actual RP06 head does not move. This causes the controller and disk to become “unsynchronized”. This behavior is tested by DSRPA TEST-270. Exiting Diagnostic Mode and executing a Recalibrate function restores synchronization. |
The RPER2 Register would normally report disk hardware status. This register is read/write but is never modified by the disk controller. This is tested by the DSRPA diagnostics.
RPxx Error Status #2 (RPER2)
RP Error Status Register #2 (RPER2) – IO Address 776740 |
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Bit(s) |
Mnemonic |
R/W |
Description |
15 |
- |
R/W |
Not used Asserted by writing a '1'. Negated by one of the following:
|
14 |
- |
R/W |
Not used Asserted by writing a '1'. Negated by one of the following:
|
13 |
PLO(PLU) |
R/W |
PLO unsafe Not implemented. Asserted by writing a '1'. Cleared by one of the following:
|
12 |
IXE |
R/W |
Index Error Not implemented. Asserted by writing a '1'. Negated by one of the following:
|
10 |
NHS |
R/W |
No Head Select Not implemented. Asserted by writing a '1'. Negated by one of the following:
|
9 |
MHS |
R/W |
Multiple Head Select Not implemented. Asserted by writing a '1'. Negated by one of the following:
|
8 |
WRU |
R/W |
Write Ready Unsafe Not implemented. Asserted by writing a '1'. Negated by one of the following:
|
7 |
ABS |
R/W |
Abnormal Stop Not implemented. Asserted by writing a '1'. Negated by one of the following:
|
6 |
TUF |
R/W |
Transitions Unsafe Not implemented. Asserted by writing a '1'. Negated by one of the following:
|
5 |
TDF |
R/W |
Transitions Detected Failure Not implemented. Asserted by writing a '1'. Negated by one of the following:
|
4 |
RAW |
R/W |
Read And Write Not implemented. Asserted by writing a '1'. Negated by one of the following:
|
3 |
CSU |
R/W |
Current Switch Unsafe Not implemented. Asserted by writing a '1'. Negated by one of the following:
|
2 |
WSU |
R/W |
Write Select Unsafe Not implemented. Asserted by writing a '1'. Negated by one of the following:
|
1 |
CSF |
R/W |
Current Sink Failure Not implemented. Asserted by writing a '1'. Negated by one of the following:
|
0 |
WCU |
R/W |
Write Current Unsafe Not implemented. Asserted by writing a '1'. Negated by one of the following:
|
The RPER3 Register would normally report error status. This register is read/write but is never modified by the disk controller. This is tested by the DSRPA diagnostics.
RPxx Error Status #3 (RPER3)
RP Error Status Register #3 (RPER3) – IO Address 776742 |
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Bit(s) |
Mnemonic |
R/W |
Description |
15 |
OCE |
R/W |
Off Cylinder Error Not implemented. Set by writing a '1' to OCE. Cleared by:
|
14 |
SKI |
R/W |
Seek Incomplete Not implemented. Set by:
Cleared by:
|
13 |
OPE |
R/W |
Unused. Set by writing a '1' to OPE. Cleared by:
|
12-7 |
- |
R/W |
Unused. Set by writing a '1' to any bits in this range. Cleared by:
|
6 |
ACL |
R/W |
AC Low Not implemented. Set by writing a '1' to ACL. Cleared by:
|
5 |
DCL |
R/W |
DC Low. Not implemented. Set by writing a '1' to DCL. Cleared by:
|
4 |
F34 |
R/W |
35V Regulator Failure Not implemented. Set by writing a '1' to F35. Cleared by:
|
3-2 |
- |
R/W |
Unused. Set by writing a '1' to any bits in this range. Cleared by:
|
1 |
VLU |
R/W |
Velocity Unsafe. Not implemented. Set by writing a '1' to VLU. Cleared by:
|
0 |
DCU |
R/W |
DC Unsafe Not implemented. Set by writing a '1' to DCU. Cleared by:
|
The ECC in the RP06 disk is a “Fire Code” with the following generator polynomial:
g(x) = x32 + x23 + x21 + x11 + x2 + 1 = (x21 + 1) (x11 + x2 + 1)
The RPEC1 Register reports the error position. The ECC (Fire Code) in the RP06 is only useful with a record length of 4644 bits or less. This is a valid assumption because the maximum RP06 record length in 18-bit mode is 4608 bits – which is 128 36-bit words. The record length is smaller in 16-bit mode.
RPxx Error Position Register (RPEC1)
RP Error Position Register (RPEC1) – IO Address 776744 |
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Bit(s) |
Mnemonic |
R/W |
Description |
15-13 |
- |
R |
Writes ignored. Always read as zero. |
12-0 |
EC1 |
R |
Not implemented. Writes ignored. Always read as zero. |
The RPEC2 Register reports error correction data. The ECC (Fire Code) in the RP06 can only correct burst errors with a length of 11 bits or less.
RPxx Error Pattern Register (RPEC2)
RP Error Pattern Register (RPEC2) – IO Address 776746 |
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Bit(s) |
Mnemonic |
R/W |
Description |
15-12 |
- |
R |
Writes ignored. Always read as zero. |
11-0 |
EC2 |
R |
Not implemented. Writes ignored. Always read as zero. |
The RH11/RPxx can execute the following commands:
Command Function Codes |
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Function Code |
Operation |
Description |
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0 |
No Op |
No op Executing a No Op sets Drive Ready (RPDS[DRY]) immediately and has no other effect. |
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1 |
Unload |
Unload On an real RPxx disk, the unload function would unload the heads, spin-down the disk, off-line the disk drive. After this operation, the operator could change the disk pack, set the disk drive back on-line, spin-up the disk, and reload the heads. Unload is not implemented on the KS10 FPGA. It should probably just set the drive offline. |
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2 |
Seek |
Seek A seek operation moves the heads to the appropriate cylinder. The seek operation is governed by three registers: the Desired Cylinder Register (RPDC), the Current Cylinder Register (RPCC), and a register that retains the simulated position of the disk head. The seek operation (or an implied seek operation) is initiated when a seek command, search command, or data transfer command (read, write, or write check) is issued and the desired cylinder register is different than the current cylinder register. The disk will not perform the seek operation if the desired cylinder is the same as the current cylinder. This is tested by DSPRA TEST-262. The disk will not preform the seek operation to an invalid address. The RP06 advertises a track-to-track seek time of 6 milliseconds and a track 0 to track 814 seek time of 53 milliseconds. In the accurate mode, the seek timing that is implemented in the KS10 FPGA is tabularized below:
When the RPXX is in Diagnostic Mode (RPMR[DMD] = '1') the disk head does not move when a seek command is issued. If the seek command is aborted by asserting a Controller Clear Command (RHCS1[CLR]), the current cylinder register is updated with the contents of the desired cylinder register. Therefore the current cylinder and the position of the disk head can become unsynchronized. A recalibrate command will restore synchronization. An Seek Incomplete error (RPER3[SKI] = '1') may only be created in Diagnostic Mode and is asserted when the current cylinder and the disk head are unsynchronized as describe above and the disk is commanded to seek off of the edge of the disk – either toward the center of the disk or toward the edge of the disk. A Seek Incomplete error also causes the controller to execute an auto-recalibrate operation. The Seek Incomplete error and auto-recalibration operation is tested by DSRPA TEST-270. |
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3 |
Recalibrate |
Recalibrate The recalibrate function drives the disk to cylinder 0 and clears the Current Cylinder register (RPCC). The recalibrate timing is the same as a seek from the current cylinder to cylinder 0. |
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4 |
Drive |
Drive Clear Resets the selected disk device only. This does not affect disk devices. The Drive Clear function clears GO (CSR1[GO]) immediately. |
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5 |
Release |
Release The release command is used by dual port operations. This command performs Drive Clear function and releases the Drive for use by the other controller. Dual port operation is not implemented so this command just performs a Drive Clear function. |
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6 |
Offset |
Offset The offset command moves the disk head off of the centerline of the track by some fraction of the track spacing (“micro”-seek) and is used to extract data from a misaligned disk pack (among other things). The amount of offset is controlled by the RPOF[OFS] bits. |
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7 |
Center |
Return to Centerline This function returns the head position back to the centerline of the track. |
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10 |
Preset |
Read-in Preset The Preset command does the following:
The Preset command is often used to initialize the device prior to bootstrap. |
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11 |
Pack Ack |
Pack Acknowledge If Composite Error is negated (RPDS[ERR] = '0'), the functions asserts Volume Valid bit in the Drive Status Register (RPDS[VV] = '1'). |
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14 |
Search |
Search A search operation occurs after the seek operation and after the head selection operation. The search operation reads the sector headers and finds a specific sector on the selected track. A search operation may include an implied seek operation. A search operation may be separate from all other operations or may be part of a data transfer operation. The search time is related to the rotation speed of the disk. The minimum search time is zero if the disk is exactly the correct position to start reading data. The maximum search time is one complete rotation of the disk. In the case of the RP06, the disk rotates at 3600 RPM; therefore the maximum search time is 16.67 milliseconds and the average search time is 8.33 milliseconds. The KS10 FPGA can simulate the disk rotation such that the sector under the head is constantly changing at a rate that is correct for the disk drive. The sector under the head is visible via the RPLA register. This is a very accurate simulation of disk rotation but is very slow. This level of simulation fidelity is required to pass some of the DSRPA diagnostics. For example: the DSRPA TEST-302 diagnostic watches the RPLA register and verifies that the sector under the head (RPLA register) is the same as the desired sector (RPDS register) when the seek operation completes. The KS10 FPGA can also simulate a seek operation as just a short time delay. This is essentially the tactic used by SIMH. This is faster but less accurate and will fail some of the diagnostic tests. The selection between the fast search operation or the accurate search operation is controlled by a conditional compile in the Verilog code. The code must be re-synthesized to change the type of seek operation. The search function can also operate in Diagnostic Mode. In Diagnostic Mode, the search operation completes when a Diagnostic Index Pulse is created via bit-banging the Diagnostic Index bit (RPMR[DIND]) of the Maintenance Register. Regardless of Diagnostic Mode, the search command completes on a Class B Error. |
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24 |
Write |
Write Check The Write Check operation does a word-by-word comparison between the contents of memory and the data read from disk drive. The status registers are update during the operation as follows:
The Write Check operation terminates when the Word Count Register (RPWC) increments to zero. When completed, the Write Check operation asserts Drive Ready (MTDS[DRY] = '1'). If a mismatch is detected, a Write Check Error is asserted (RPCS2[WCE] = '1'). Note: as far as the disk drive is concerned, a Write Check operation is identical to a Read operation. The comparison is handled in the RH11. |
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25 |
Write |
Write Check Header I don't actually know how this works or if this is used for anything. It does not seem necessary for the diagnostic programs. When completed, the Write Check Header operation asserts Drive Ready (MTDS[DRY] = '1'). |
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30 |
Write |
Write The Write operation reads data from memory and transfers the data to the disk drive. The status registers are updated during the operation as follows:
The Write operation terminates when the Word Count Register (RPWC) increments to zero. If a partial sector is written, the remainder of the sector is written with zeros. When completed, the Write operation asserts Drive Ready (MTDS[DRY] = '1'). |
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31 |
Write |
Write Header On a real disk drive, the Write Header operation is used during the disk format process to write the sector header onto the disk pack. On the KS10, the parts of Write Header operation is implemented which saves the sector data to a RAM Buffer in order to pass some diagnostics. When completed, the Write Header operation asserts Drive Ready (MTDS[DRY] = '1'). |
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34 |
Read |
Read The Read Forward operation reads data from the Disk Drive and transfers the data to memory. The status registers are updated during the operation as follows:
The Read operation terminates when the Word Count Register (RPWC) increments to zero.
When completed, the Read command asserts Drive Ready (MTDS[DRY] = '1'). Note: when a read of a partial sector is requested, only the requested data is written to memory. Whether or not the whole sector is read from the disk drive is unknown and is invisible to the system. |
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35 |
Read |
Read Header On a real disk drive, the Read Header operation is used to readback the sector header off of the disk pack to verify that it is correct. On the KS10, the parts of Read Header operation is implemented which can readback the sector data from a RAM Buffer in order to pass some diagnostics. When completed, the Read Header operation asserts Drive Ready (MTDS[DRY] = '1'). |
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The RH11 Massbus Controller and RP06 Disk array appears to be working.
There may be minor issues with interrupts as this is probably not tested by the DSRPA diagnostics.
The diagnostic status of the RH11 and RP06 is summarized below:
DIAGNOSTIC Result ---------------------------------------------------------------- ------ DSRPAC0 DECSYSTEM 2020 KS10/RH11 - RP06 BASIC DEVICE DIAGNOSTIC Pass DSRMB0 DECSYSTEM 2020 RH11 - RM03/RP06 - RELIABILITY DIAGNOSTIC Fail
Click on the underlined Pass/Fail issues links in the table above for more information regarding status.
* SMMON [DSQDC] - DECSYSTEM 2020 DIAGNOSTIC MONITOR - VER 0.3 *
SMMON CMD - DSRMB
DSRMB - DECSYSTEM 2020 RH11 - RM03/RP06 - RELIABILITY DIAGNOSTIC
VERSION 0.2, SV=0.3, CPU#=4097, MCV=130, MCO=470, HO=0, KASW=003740 000000
TTY SWITCH CONTROL ? - 0,S OR Y <CR> - Y
LH SWITCHES <# OR ?> - 10
RH SWITCHES <# OR ?> - 20000
SWITCHES = 000010 020000
MEMORY MAP =
FROM TO SIZE/K
00000000 03777777 1024
RH11 - 1 - MASSBUS CONFIGURATION
DRIVE - STATUS OF UNIT FOUND
0 - RP06, DRIVE SER. NO.=0011., (OFFLINE)
1 - RP06, DRIVE SER. NO.=0012., (OFFLINE)
2 - RP06, DRIVE SER. NO.=0013., (ONLINE), WRT PROTECTED
*** 11 FORMATTED BY, DRIVE SER. NO.=0000.,
NAME ID TYPE
3 - RP06, DRIVE SER. NO.=0014., (OFFLINE)
4 - RP06, DRIVE SER. NO.=0015., (OFFLINE)
5 - RP06, DRIVE SER. NO.=0016., (OFFLINE)
6 - RP06, DRIVE SER. NO.=0017., (ONLINE), WRT ENABLED
*** 10 FORMATTED BY, DRIVE SER. NO.=0000.,
NAME ID TYPE
7 - RP06, DRIVE SER. NO.=0018., (ONLINE), WRT ENABLED
*** 10 FORMATTED BY, DRIVE SER. NO.=0000.,
NAME ID TYPE
WHAT DRIVE(S) TO BE TESTED (00 TO 77, ALL, H=HELP)? - 7
TYPE "H" FOR TEST NAME HELP MESSAGE
WHAT TEST ? - 13
PTIME
POSITION TIMING TESTS - ALL TIMES IN MILLISECONDS
DRIVE HIGH LOW RANGE AVERAGE
----- ---- --- ----- -------
ROTATIONAL VELOCITY
07 2.3 1.8 0.5 1.9
RECALIBRATE TEST - 100. ITERATIONS
07 0.0 0.0 0.0 0.0
ALL SINGLE CYLINDER FORWARD SEEKS
07 5.0 5.0 0.0 5.0
ALL SINGLE CYLINDER REVERSE SEEKS
07 5.0 5.0 0.0 5.0
INCREMENTAL FORWARD SEEKS
07 50.1 5.0 45.0 43.8
INCREMENTAL REVERSE SEEKS
07 50.1 5.0 45.0 43.8
500. RANDOM SEEKS
07 50.1 5.0 45.0 40.4
AVERAGE SEEK TIME - 100. ITERATIONS
07 40.0 40.0 0.0 40.0
MAXIMUM SEEK TIME - 100. ITERATIONS
07 50.1 50.1 0.0 50.1
====================
WHAT TEST ? -