The DEC KS10 - A classic look

KS10 FPGA in Mini-ITX chassis

The goal of this project is to re-implement the DEC KS10 using modern components and technology. It is intended that this will closely, but not exactly, replicate the KS10 design in FPGA hardware. I have no desire to exactly replicate the KS10 timing: there are too many places where the logic is difficult to replicate. The DEC KS10 used a lot of asynchronous parts (asynchronous memory, asynchronous logic, FIFOs/SILOs, one-shots, delay lines, RC delays, etc) that don't map very well to modern components - especially FPGAs. I've elected to redesign circuitry as necessary to use the FPGA resources. This project will retain microcode compatibility with the DEC KS10.

The DEC KS10 was implemented in 1978 using AMD am29xx TTL bit-slice device and 74LSxx SSI and MSI devices. The DEC KS10 had a 6.66 MHz clock cycle.

The DEC KS10 consisted of the following circuit boards:

• 4 board CPU set
• Console based on Intel 8080 microprocessor
• Memory Controller
• 8 Memory boards (64K x 36 with ECC)
• 2 (or more) Unibus Adapters
• Disk IO (RH11/RP)
• TTY IO (DZ11)
• Tape Unit (RH11/TM03/TU)
• Power Supply

In addition to implementing these basic functions, the KS10 FPGA implements:

• Synchronous COM Unit (DUP11)
• General Purpose Processor (KMC11)
• Printer controller and printer (LP20/LP26)
• 3rd Unibus Adapter (UBA4)
• Unibus Exercisers

The CPU, Console, Memory Controller, and Unibus Adapters boards are all interconnected by the KS10 backplane bus.

The Console Processor and the entire KS10 Central Processing Unit (CPU) is implemented in a single Intel Cyclone 5 System on a Chip (SoC) Field Programmable Gate Array (FPGA). In addition to the FPGA, this SoC includes a dual core ARM processor which provides the platform for the Console Processor and provides capabilities for modern networking. The FPGA is firmware is written in Verilog and currently consists of about 33,000 lines of code plus comments. The Console Software is multi-threaded Linux application that is written in C++.

The KS10 FPGA peripherals are significantly different than the legacy DEC KS10 peripherals. Modern peripherals like Secure Digital High-Capacity (SDHC) solid-state disk drives replace the Moving Head RP06 disk drives and TU77 9-track magtape drives. Even though the physical devices are different, the original hardware interfaces have been retained. The disk drives use the same bits-on-disk formatting as the SIMH simulator so that files and disk images may be moved between SIMH and the target hardware without modification. Universal Serial Bus (USB) and Ethernet devices are provided in addition to standard legacy RS-232 devices.

The latest revision of the KS10 FPGA Processor Manual is available from: KS10 FPGA Processor Manual (Rev 47) Please note that the Processor Manual is not actively maintained as most of the documentation has been shifted to this WIKI.

DSKAAA0 DECSYSTEM 2020 BASIC INSTRUCTION DIAGNOSTIC ( 1) . . . . . . . . . . . . Pass
DSKABA0 DECSYSTEM 2020 BASIC INSTRUCTION DIAGNOSTIC ( 2) . . . . . . . . . . . . Pass
DSKACA0 DECSYSTEM 2020 BASIC INSTRUCTION DIAGNOSTIC ( 3) . . . . . . . . . . . . Pass
DSKADA0 DECSYSTEM 2020 BASIC INSTRUCTION DIAGNOSTIC ( 4) . . . . . . . . . . . . Pass
DSKAEA0 DECSYSTEM 2020 BASIC INSTRUCTION DIAGNOSTIC ( 5) . . . . . . . . . . . . Pass
DSKAFA0 DECSYSTEM 2020 BASIC INSTRUCTION DIAGNOSTIC ( 6) . . . . . . . . . . . . Pass
DSKAGA0 DECSYSTEM 2020 BASIC INSTRUCTION DIAGNOSTIC ( 7) . . . . . . . . . . . . Pass
DSKAHA0 DECSYSTEM 2020 BASIC INSTRUCTION DIAGNOSTIC ( 8) . . . . . . . . . . . . Pass
DSKAIA0 DECSYSTEM 2020 BASIC INSTRUCTION DIAGNOSTIC ( 9) . . . . . . . . . . . . Pass
DSKAJA0 DECSYSTEM 2020 BASIC INSTRUCTION DIAGNOSTIC (10) . . . . . . . . . . . . Pass
DSKAKA0 DECSYSTEM 2020 BASIC INSTRUCTION DIAGNOSTIC (11) . . . . . . . . . . . . Pass
DSKALA0 DECSYSTEM 2020 BASIC INSTRUCTION DIAGNOSTIC (12) . . . . . . . . . . . . Pass
DSKAMA0 DECSYSTEM 2020 BASIC INSTRUCTION DIAGNOSTIC (13) . . . . . . . . . . . . Pass
DSKBAA0 DECSYSTEM 2020 BASIC INSTRUCTION RELIABILITY DIAGNOSTIC  . . . . . . . . Pass
DSKCAA0 DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC (1) . . . . . . . . . . . Pass
DSKCBA0 DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC (2) . . . . . . . . . . . Pass
DSKCCA0 DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC (3) . . . . . . . . . . . Pass
DSKCDA0 DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC (4) . . . . . . . . . . . Pass
DSKCEA0 DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC (5) . . . . . . . . . . . Pass
DSKCFC0 DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC (6) . . . . . . . . . . . Pass
DSKCGB0 DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC (7) . . . . . . . . . . . . . Fail
DSKDAB0 DECSYSTEM 2020 CPU AND MEMORY RELIABILITY DIAGNOSTIC . . . . . . . . . . . . Fail
DSKEAA0 DECSYSTEM 2020 PAGING HARDWARE DIAGNOSTIC  . . . . . . . . . . . . . . . . . Fail
DSKEBA0 KS10 - CACHE DIAGNOSTIC  . . . . . . . . . . . . . . . . . . . . . . . . Pass*
DSKECB0 KS10 - KL-PAGING DIAGNOSTIC  . . . . . . . . . . . . . . . . . . . . . . . . Fail
DSKFAA0 DECSYSTEM 2020 INSTRUCTION TIMING DIAGNOSTIC . . . . . . . . . . . . . . Pass
DSDUAB0 DSDUA DECSYSTEM 2020 DUP-11 DIAGNOSTICS  . . . . . . . . . . . . . . . . Pass
DSDZAB0 DECSYSTEM 2020 DZ11 ASYNC. LINE MUX DIAGNOSTICS (DSDZA). . . . . . . . . Pass
DSKMAA0 DECSYSTEM 2020 KMC11 DIAGNOSTICS . . . . . . . . . . . . . . . . . . . . Pass
DSLPA   DECSYSTEM 2020 LINE PRINTER DIAGNOSTIC [DSLPA] . . . . . . . . . . . . . Pass
DSLTA   DECSYSTEM 2020 TELETYPE TEST . . . . . . . . . . . . . . . . . . . . . . Pass
DSMMAB0 DECSYSTEM 2020 KS10 1024K MEMORY DIAGNOSTIC (DSMMA)  . . . . . . . . . . Pass
DSMMBA0 DECSYSTEM 2020 BLT/FLOATING 1-0 MEMORY EXERCISER TEST (DSMMB)  . . . . . Pass
DSMMCB0 DECSYSTEM 2020 FAST AC DIAGNOSTIC (DSMMC)  . . . . . . . . . . . . . . . Pass
DSMMDC0 DECSYSTEM 2020 MEMORY DIAGNOSTIC (DSMMD) . . . . . . . . . . . . . . . . Pass
DSRMAB0 DECSYSTEM 2020 RM03-RH11 BASIC DRIVE DIAGNOSTIC  . . . . . . . . . . . . . . Fail
DSRMB   DECSYSTEM 2020 RH11 - RM03/RP06 - RELIABILITY DIAGNOSTIC . . . . . . . . . . Fail
DSRPAC0 DECSYSTEM 2020 RP06-RH11 BASIC DRIVE DIAGNOSTIC [DSRPA]  . . . . . . . . Pass**
DSTUA   DECSYSTEM 2020 RH11-TM02/03-TU45/TU77 BASIC DEVICE DIAGNOSTIC (DSTUA)  . . . Fail
DSTUB   DECSYSTEM 2020 RH11-TM02/03-TU16/TU45/TU77 RELIABILITY DIAGNOSTIC(DSTUB) Pass
DSUBAC0 DECSYSTEM 2020 UNIBUS ADAPTER EXERCISER  [ DSUBA ] . . . . . . . . . . . Pass

* This includes expected failures because the cache is not implemented. The FPGA main memory uses very fast Synchronous SRAM that can perform reads and writes in a single CPU clock cycle - just like a cache.

** This includes expected failures because parts of the RP06 Diagnostic Mode is not implemented. The RP06 Diagnostic Mode is only used by the diagnostic program and is not required for any of the Monitor programs.

The KS10 Hardware Documents (schematics) are available from: http://www.bitsavers.org/pdf/dec/pdp10/KS10/

KS10 Software is available from: http://pdp-10.trailing-edge.com/